\doxysection{core\+\_\+armv81mml.\+h}
\hypertarget{core__armv81mml_8h_source}{}\label{core__armv81mml_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_armv81mml.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_armv81mml.h}}
\mbox{\hyperlink{core__armv81mml_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{00001\ \textcolor{comment}{/**************************************************************************/}}
\DoxyCodeLine{00007\ \textcolor{comment}{/*}}
\DoxyCodeLine{00008\ \textcolor{comment}{\ *\ Copyright\ (c)\ 2018-\/2019\ Arm\ Limited.\ All\ rights\ reserved.}}
\DoxyCodeLine{00009\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00010\ \textcolor{comment}{\ *\ SPDX-\/License-\/Identifier:\ Apache-\/2.0}}
\DoxyCodeLine{00011\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00012\ \textcolor{comment}{\ *\ Licensed\ under\ the\ Apache\ License,\ Version\ 2.0\ (the\ License);\ you\ may}}
\DoxyCodeLine{00013\ \textcolor{comment}{\ *\ not\ use\ this\ file\ except\ in\ compliance\ with\ the\ License.}}
\DoxyCodeLine{00014\ \textcolor{comment}{\ *\ You\ may\ obtain\ a\ copy\ of\ the\ License\ at}}
\DoxyCodeLine{00015\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00016\ \textcolor{comment}{\ *\ www.apache.org/licenses/LICENSE-\/2.0}}
\DoxyCodeLine{00017\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00018\ \textcolor{comment}{\ *\ Unless\ required\ by\ applicable\ law\ or\ agreed\ to\ in\ writing,\ software}}
\DoxyCodeLine{00019\ \textcolor{comment}{\ *\ distributed\ under\ the\ License\ is\ distributed\ on\ an\ AS\ IS\ BASIS,\ WITHOUT}}
\DoxyCodeLine{00020\ \textcolor{comment}{\ *\ WARRANTIES\ OR\ CONDITIONS\ OF\ ANY\ KIND,\ either\ express\ or\ implied.}}
\DoxyCodeLine{00021\ \textcolor{comment}{\ *\ See\ the\ License\ for\ the\ specific\ language\ governing\ permissions\ and}}
\DoxyCodeLine{00022\ \textcolor{comment}{\ *\ limitations\ under\ the\ License.}}
\DoxyCodeLine{00023\ \textcolor{comment}{\ */}}
\DoxyCodeLine{00024\ }
\DoxyCodeLine{00025\ \textcolor{preprocessor}{\#if\ \ \ defined\ (\ \_\_ICCARM\_\_\ )}}
\DoxyCodeLine{00026\ \textcolor{preprocessor}{\ \ \#pragma\ system\_include\ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ for\ MISRA\ check\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00027\ \textcolor{preprocessor}{\#elif\ defined\ (\_\_clang\_\_)}}
\DoxyCodeLine{00028\ \textcolor{preprocessor}{\ \ \#pragma\ clang\ system\_header\ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00029\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00030\ }
\DoxyCodeLine{00031\ \textcolor{preprocessor}{\#ifndef\ \_\_CORE\_ARMV81MML\_H\_GENERIC}}
\DoxyCodeLine{00032\ \textcolor{preprocessor}{\#define\ \_\_CORE\_ARMV81MML\_H\_GENERIC}}
\DoxyCodeLine{00033\ }
\DoxyCodeLine{00034\ \textcolor{preprocessor}{\#include\ <stdint.h>}}
\DoxyCodeLine{00035\ }
\DoxyCodeLine{00036\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00037\ \ \textcolor{keyword}{extern}\ \textcolor{stringliteral}{"{}C"{}}\ \{}
\DoxyCodeLine{00038\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00039\ }
\DoxyCodeLine{00053\ }
\DoxyCodeLine{00054\ }
\DoxyCodeLine{00055\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{00056\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CMSIS\ definitions}}
\DoxyCodeLine{00057\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{00062\ }
\DoxyCodeLine{00063\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{cmsis__version_8h}{cmsis\_version.h}}"{}}}
\DoxyCodeLine{00064\ \ }
\DoxyCodeLine{00065\ \textcolor{preprocessor}{\#define\ \_\_ARM\_ARCH\_8M\_MAIN\_\_\ \ \ \ 1\ \ }\textcolor{comment}{//\ patching\ for\ now}}
\DoxyCodeLine{00066\ \textcolor{comment}{/*\ \ CMSIS\ ARMV81MML\ definitions\ */}}
\DoxyCodeLine{00067\ \textcolor{preprocessor}{\#define\ \_\_ARMv81MML\_CMSIS\_VERSION\_MAIN\ \ (\_\_CM\_CMSIS\_VERSION\_MAIN)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00068\ \textcolor{preprocessor}{\#define\ \_\_ARMv81MML\_CMSIS\_VERSION\_SUB\ \ \ (\_\_CM\_CMSIS\_VERSION\_SUB)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00069\ \textcolor{preprocessor}{\#define\ \_\_ARMv81MML\_CMSIS\_VERSION\ \ \ \ \ \ \ ((\_\_ARMv81MML\_CMSIS\_VERSION\_MAIN\ <<\ 16U)\ |\ \(\backslash\)}}
\DoxyCodeLine{00070\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_ARMv81MML\_CMSIS\_VERSION\_SUB\ \ \ \ \ \ \ \ \ \ \ )\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00071\ }
\DoxyCodeLine{00072\ \textcolor{preprocessor}{\#define\ \_\_CORTEX\_M\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (81U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00073\ }
\DoxyCodeLine{00077\ \textcolor{preprocessor}{\#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{00078\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_TARGET\_FPU\_VFP}}
\DoxyCodeLine{00079\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00080\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00081\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00082\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00083\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00084\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00085\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00086\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00087\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00088\ }
\DoxyCodeLine{00089\ \textcolor{preprocessor}{\ \ \#if\ defined(\_\_ARM\_FEATURE\_DSP)}}
\DoxyCodeLine{00090\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined(\_\_DSP\_PRESENT)\ \&\&\ (\_\_DSP\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00091\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00092\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00093\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ DSP\ (SIMD)\ instructions\ for\ a\ devices\ without\ DSP\ extensions\ (check\ \_\_DSP\_PRESENT)"{}}}
\DoxyCodeLine{00094\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U\ \ \ \ }}
\DoxyCodeLine{00095\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00096\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00097\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00098\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00099\ \ \ }
\DoxyCodeLine{00100\ \textcolor{preprocessor}{\#elif\ defined\ (\_\_ARMCC\_VERSION)\ \&\&\ (\_\_ARMCC\_VERSION\ >=\ 6010050)}}
\DoxyCodeLine{00101\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_ARM\_FP}}
\DoxyCodeLine{00102\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00103\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00104\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00105\ \textcolor{preprocessor}{\ \ \ \ \ \ \#warning\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00106\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00107\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00108\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00109\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00110\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00111\ }
\DoxyCodeLine{00112\ \textcolor{preprocessor}{\ \ \#if\ defined(\_\_ARM\_FEATURE\_DSP)}}
\DoxyCodeLine{00113\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined(\_\_DSP\_PRESENT)\ \&\&\ (\_\_DSP\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00114\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00115\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00116\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ DSP\ (SIMD)\ instructions\ for\ a\ devices\ without\ DSP\ extensions\ (check\ \_\_DSP\_PRESENT)"{}}}
\DoxyCodeLine{00117\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U\ \ \ \ }}
\DoxyCodeLine{00118\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00119\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00120\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00121\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00122\ }
\DoxyCodeLine{00123\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_GNUC\_\_\ )}}
\DoxyCodeLine{00124\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_VFP\_FP\_\_)\ \&\&\ !defined(\_\_SOFTFP\_\_)}}
\DoxyCodeLine{00125\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00126\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00127\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00128\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00129\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00130\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00131\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00132\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00133\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00134\ \ \ }
\DoxyCodeLine{00135\ \textcolor{preprocessor}{\ \ \#if\ defined(\_\_ARM\_FEATURE\_DSP)}}
\DoxyCodeLine{00136\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined(\_\_DSP\_PRESENT)\ \&\&\ (\_\_DSP\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00137\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00138\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00139\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ DSP\ (SIMD)\ instructions\ for\ a\ devices\ without\ DSP\ extensions\ (check\ \_\_DSP\_PRESENT)"{}}}
\DoxyCodeLine{00140\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U\ \ \ \ }}
\DoxyCodeLine{00141\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00142\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00143\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00144\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00145\ \ \ }
\DoxyCodeLine{00146\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_ICCARM\_\_\ )}}
\DoxyCodeLine{00147\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_ARMVFP\_\_}}
\DoxyCodeLine{00148\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00149\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00150\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00151\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00152\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00153\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00154\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00155\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00156\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00157\ }
\DoxyCodeLine{00158\ \textcolor{preprocessor}{\ \ \#if\ defined(\_\_ARM\_FEATURE\_DSP)}}
\DoxyCodeLine{00159\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined(\_\_DSP\_PRESENT)\ \&\&\ (\_\_DSP\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00160\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00161\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00162\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ DSP\ (SIMD)\ instructions\ for\ a\ devices\ without\ DSP\ extensions\ (check\ \_\_DSP\_PRESENT)"{}}}
\DoxyCodeLine{00163\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U\ \ \ \ }}
\DoxyCodeLine{00164\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00165\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00166\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DSP\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00167\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00168\ \ \ }
\DoxyCodeLine{00169\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_TI\_ARM\_\_\ )}}
\DoxyCodeLine{00170\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_TI\_VFP\_SUPPORT\_\_}}
\DoxyCodeLine{00171\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00172\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00173\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00174\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00175\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00176\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00177\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00178\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00179\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00180\ }
\DoxyCodeLine{00181\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_TASKING\_\_\ )}}
\DoxyCodeLine{00182\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_FPU\_VFP\_\_}}
\DoxyCodeLine{00183\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00184\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00185\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00186\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00187\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00188\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00189\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00190\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00191\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00192\ }
\DoxyCodeLine{00193\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_CSMC\_\_\ )}}
\DoxyCodeLine{00194\ \textcolor{preprocessor}{\ \ \#if\ (\ \_\_CSMC\_\_\ \&\ 0x400U)}}
\DoxyCodeLine{00195\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00196\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00197\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00198\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00199\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00200\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00201\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00202\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00203\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00204\ }
\DoxyCodeLine{00205\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00206\ }
\DoxyCodeLine{00207\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{cmsis__compiler_8h}{cmsis\_compiler.h}}"{}}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ CMSIS\ compiler\ specific\ defines\ */}}
\DoxyCodeLine{00208\ }
\DoxyCodeLine{00209\ }
\DoxyCodeLine{00210\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00211\ \}}
\DoxyCodeLine{00212\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00213\ }
\DoxyCodeLine{00214\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CORE\_ARMV81MML\_H\_GENERIC\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00215\ }
\DoxyCodeLine{00216\ \textcolor{preprocessor}{\#ifndef\ \_\_CMSIS\_GENERIC}}
\DoxyCodeLine{00217\ }
\DoxyCodeLine{00218\ \textcolor{preprocessor}{\#ifndef\ \_\_CORE\_ARMV81MML\_H\_DEPENDANT}}
\DoxyCodeLine{00219\ \textcolor{preprocessor}{\#define\ \_\_CORE\_ARMV81MML\_H\_DEPENDANT}}
\DoxyCodeLine{00220\ }
\DoxyCodeLine{00221\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00222\ \ \textcolor{keyword}{extern}\ \textcolor{stringliteral}{"{}C"{}}\ \{}
\DoxyCodeLine{00223\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00224\ }
\DoxyCodeLine{00225\ \textcolor{comment}{/*\ check\ device\ defines\ and\ use\ defaults\ */}}
\DoxyCodeLine{00226\ \textcolor{preprocessor}{\#if\ defined\ \_\_CHECK\_DEVICE\_DEFINES}}
\DoxyCodeLine{00227\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_ARMv81MML\_REV}}
\DoxyCodeLine{00228\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_ARMv81MML\_REV\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x0000U}}
\DoxyCodeLine{00229\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_ARMv81MML\_REV\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00230\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00231\ }
\DoxyCodeLine{00232\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_FPU\_PRESENT}}
\DoxyCodeLine{00233\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00234\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_FPU\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00235\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00236\ }
\DoxyCodeLine{00237\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_MPU\_PRESENT}}
\DoxyCodeLine{00238\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_MPU\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00239\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_MPU\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00240\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00241\ }
\DoxyCodeLine{00242\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_SAUREGION\_PRESENT}}
\DoxyCodeLine{00243\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_SAUREGION\_PRESENT\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00244\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_SAUREGION\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00245\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00246\ }
\DoxyCodeLine{00247\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_DSP\_PRESENT}}
\DoxyCodeLine{00248\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DSP\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00249\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_DSP\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00250\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00251\ }
\DoxyCodeLine{00252\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_NVIC\_PRIO\_BITS}}
\DoxyCodeLine{00253\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_NVIC\_PRIO\_BITS\ \ \ \ \ \ \ \ \ \ 3U}}
\DoxyCodeLine{00254\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_NVIC\_PRIO\_BITS\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00255\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00256\ }
\DoxyCodeLine{00257\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_Vendor\_SysTickConfig}}
\DoxyCodeLine{00258\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_Vendor\_SysTickConfig\ \ \ \ 0U}}
\DoxyCodeLine{00259\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_Vendor\_SysTickConfig\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00260\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00261\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00262\ }
\DoxyCodeLine{00263\ \textcolor{comment}{/*\ IO\ definitions\ (access\ restrictions\ to\ peripheral\ registers)\ */}}
\DoxyCodeLine{00271\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00272\ \textcolor{preprocessor}{\ \ \#define\ \ \ \_\_I\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00273\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00274\ \textcolor{preprocessor}{\ \ \#define\ \ \ \_\_I\ \ \ \ \ volatile\ const\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00275\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00276\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_O\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00277\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IO\ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00278\ }
\DoxyCodeLine{00279\ \textcolor{comment}{/*\ following\ defines\ should\ be\ used\ for\ structure\ members\ */}}
\DoxyCodeLine{00280\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IM\ \ \ \ \ volatile\ const\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00281\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_OM\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00282\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IOM\ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00283\ }
\DoxyCodeLine{00285\ }
\DoxyCodeLine{00286\ }
\DoxyCodeLine{00287\ }
\DoxyCodeLine{00288\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{00289\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Register\ Abstraction}}
\DoxyCodeLine{00290\ \textcolor{comment}{\ \ Core\ Register\ contain:}}
\DoxyCodeLine{00291\ \textcolor{comment}{\ \ -\/\ Core\ Register}}
\DoxyCodeLine{00292\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Register}}
\DoxyCodeLine{00293\ \textcolor{comment}{\ \ -\/\ Core\ SCB\ Register}}
\DoxyCodeLine{00294\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Register}}
\DoxyCodeLine{00295\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Register}}
\DoxyCodeLine{00296\ \textcolor{comment}{\ \ -\/\ Core\ MPU\ Register}}
\DoxyCodeLine{00297\ \textcolor{comment}{\ \ -\/\ Core\ SAU\ Register}}
\DoxyCodeLine{00298\ \textcolor{comment}{\ \ -\/\ Core\ FPU\ Register}}
\DoxyCodeLine{00299\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{00304\ }
\DoxyCodeLine{00311\ }
\DoxyCodeLine{00315\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00316\ \{}
\DoxyCodeLine{00317\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00318\ \ \ \{}
\DoxyCodeLine{00319\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gafbce95646fd514c10aa85ec0a33db728}{\_reserved0}}:16;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00320\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadcb98a5b9c93b0cb69cdb7af5638f32e}{GE}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00321\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac681f266e20b3b3591b961e13633ae13}{\_reserved1}}:7;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00322\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga22d10913489d24ab08bd83457daa88de}{Q}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00323\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8004d224aacb78ca37774c35f9156e7e}{V}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00324\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga86e2c5b891ecef1ab55b1edac0da79a6}{C}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00325\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3b04d58738b66a28ff13f23d8b0ba7e5}{Z}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00326\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7e7bbba9b00b0bb3283dc07f1abe37e0}{N}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00327\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00328\ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae4c2ef8c9430d7b7bef5cbfbbaed3a94}{w}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00329\ \}\ \mbox{\hyperlink{union_a_p_s_r___type}{APSR\_Type}};}
\DoxyCodeLine{00330\ }
\DoxyCodeLine{00331\ \textcolor{comment}{/*\ APSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00332\ \textcolor{preprocessor}{\#define\ APSR\_N\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00333\ \textcolor{preprocessor}{\#define\ APSR\_N\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_N\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00334\ }
\DoxyCodeLine{00335\ \textcolor{preprocessor}{\#define\ APSR\_Z\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00336\ \textcolor{preprocessor}{\#define\ APSR\_Z\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_Z\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00337\ }
\DoxyCodeLine{00338\ \textcolor{preprocessor}{\#define\ APSR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00339\ \textcolor{preprocessor}{\#define\ APSR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00340\ }
\DoxyCodeLine{00341\ \textcolor{preprocessor}{\#define\ APSR\_V\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00342\ \textcolor{preprocessor}{\#define\ APSR\_V\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_V\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00343\ }
\DoxyCodeLine{00344\ \textcolor{preprocessor}{\#define\ APSR\_Q\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00345\ \textcolor{preprocessor}{\#define\ APSR\_Q\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_Q\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00346\ }
\DoxyCodeLine{00347\ \textcolor{preprocessor}{\#define\ APSR\_GE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00348\ \textcolor{preprocessor}{\#define\ APSR\_GE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ APSR\_GE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00349\ }
\DoxyCodeLine{00350\ }
\DoxyCodeLine{00354\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00355\ \{}
\DoxyCodeLine{00356\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00357\ \ \ \{}
\DoxyCodeLine{00358\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab46e5f1b2f4d17cfb9aca4fffcbb2fa5}{ISR}}:9;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00359\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad2eb0a06de4f03f58874a727716aa9aa}{\_reserved0}}:23;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00360\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00361\ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4adca999d3a0bc1ae682d73ea7cfa879}{w}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00362\ \}\ \mbox{\hyperlink{union_i_p_s_r___type}{IPSR\_Type}};}
\DoxyCodeLine{00363\ }
\DoxyCodeLine{00364\ \textcolor{comment}{/*\ IPSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00365\ \textcolor{preprocessor}{\#define\ IPSR\_ISR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00366\ \textcolor{preprocessor}{\#define\ IPSR\_ISR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ IPSR\_ISR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00367\ }
\DoxyCodeLine{00368\ }
\DoxyCodeLine{00372\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00373\ \{}
\DoxyCodeLine{00374\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00375\ \ \ \{}
\DoxyCodeLine{00376\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3e9120dcf1a829fc8d2302b4d0673970}{ISR}}:9;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00377\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf438e0f407357e914a70b5bd4d6a97c5}{\_reserved0}}:7;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00378\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2d0ec4ccae337c1df5658f8cf4632e76}{GE}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00379\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga790056bb6f20ea16cecc784b0dd19ad6}{\_reserved1}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00380\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7eed9fe24ae8d354cd76ae1c1110a658}{T}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00381\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3200966922a194d84425e2807a7f1328}{IT}}:2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00382\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadd7cbd2b0abd8954d62cd7831796ac7c}{Q}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00383\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf14df16ea0690070c45b95f2116b7a0a}{V}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00384\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga40213a6b5620410cac83b0d89564609d}{C}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00385\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga1e5d9801013d5146f2e02d9b7b3da562}{Z}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00386\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2db9a52f6d42809627d1a7a607c5dbc5}{N}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00387\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00388\ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga1a47176768f45f79076c4f5b1b534bc2}{w}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00389\ \}\ \mbox{\hyperlink{unionx_p_s_r___type}{xPSR\_Type}};}
\DoxyCodeLine{00390\ }
\DoxyCodeLine{00391\ \textcolor{comment}{/*\ xPSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00392\ \textcolor{preprocessor}{\#define\ xPSR\_N\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00393\ \textcolor{preprocessor}{\#define\ xPSR\_N\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_N\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00394\ }
\DoxyCodeLine{00395\ \textcolor{preprocessor}{\#define\ xPSR\_Z\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00396\ \textcolor{preprocessor}{\#define\ xPSR\_Z\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_Z\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00397\ }
\DoxyCodeLine{00398\ \textcolor{preprocessor}{\#define\ xPSR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00399\ \textcolor{preprocessor}{\#define\ xPSR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00400\ }
\DoxyCodeLine{00401\ \textcolor{preprocessor}{\#define\ xPSR\_V\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00402\ \textcolor{preprocessor}{\#define\ xPSR\_V\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_V\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00403\ }
\DoxyCodeLine{00404\ \textcolor{preprocessor}{\#define\ xPSR\_Q\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00405\ \textcolor{preprocessor}{\#define\ xPSR\_Q\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_Q\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00406\ }
\DoxyCodeLine{00407\ \textcolor{preprocessor}{\#define\ xPSR\_IT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00408\ \textcolor{preprocessor}{\#define\ xPSR\_IT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ xPSR\_IT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00409\ }
\DoxyCodeLine{00410\ \textcolor{preprocessor}{\#define\ xPSR\_T\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00411\ \textcolor{preprocessor}{\#define\ xPSR\_T\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_T\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00412\ }
\DoxyCodeLine{00413\ \textcolor{preprocessor}{\#define\ xPSR\_GE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00414\ \textcolor{preprocessor}{\#define\ xPSR\_GE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ xPSR\_GE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00415\ }
\DoxyCodeLine{00416\ \textcolor{preprocessor}{\#define\ xPSR\_ISR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00417\ \textcolor{preprocessor}{\#define\ xPSR\_ISR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ xPSR\_ISR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00418\ }
\DoxyCodeLine{00419\ }
\DoxyCodeLine{00423\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00424\ \{}
\DoxyCodeLine{00425\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00426\ \ \ \{}
\DoxyCodeLine{00427\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga35c1732cf153b7b5c4bd321cf1de9605}{nPRIV}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00428\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8cc085fea1c50a8bd9adea63931ee8e2}{SPSEL}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00429\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac62cfff08e6f055e0101785bad7094cd}{FPCA}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00430\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadab539fdfb991718401475bf6853669c}{SFPA}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00431\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa7a5662079a447f801034d108f80ce49}{\_reserved1}}:28;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00432\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00433\ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6b642cca3d96da660b1198c133ca2a1f}{w}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00434\ \}\ \mbox{\hyperlink{union_c_o_n_t_r_o_l___type}{CONTROL\_Type}};}
\DoxyCodeLine{00435\ }
\DoxyCodeLine{00436\ \textcolor{comment}{/*\ CONTROL\ Register\ Definitions\ */}}
\DoxyCodeLine{00437\ \textcolor{preprocessor}{\#define\ CONTROL\_SFPA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00438\ \textcolor{preprocessor}{\#define\ CONTROL\_SFPA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CONTROL\_SFPA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00439\ }
\DoxyCodeLine{00440\ \textcolor{preprocessor}{\#define\ CONTROL\_FPCA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00441\ \textcolor{preprocessor}{\#define\ CONTROL\_FPCA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CONTROL\_FPCA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00442\ }
\DoxyCodeLine{00443\ \textcolor{preprocessor}{\#define\ CONTROL\_SPSEL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00444\ \textcolor{preprocessor}{\#define\ CONTROL\_SPSEL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CONTROL\_SPSEL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00445\ }
\DoxyCodeLine{00446\ \textcolor{preprocessor}{\#define\ CONTROL\_nPRIV\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00447\ \textcolor{preprocessor}{\#define\ CONTROL\_nPRIV\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ CONTROL\_nPRIV\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00448\ }
\DoxyCodeLine{00450\ }
\DoxyCodeLine{00451\ }
\DoxyCodeLine{00458\ }
\DoxyCodeLine{00462\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00463\ \{}
\DoxyCodeLine{00464\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga06726c729c5557701defc4d6b5d8f9f6}{ISER}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00465\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[16U];}
\DoxyCodeLine{00466\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaed882e10ea8ee6a915007af71643d7da}{ICER}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00467\ \ \ \ \ \ \ \ \ uint32\_t\ RSERVED1[16U];}
\DoxyCodeLine{00468\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga288bc5e8b844a531a6ecdcc8dbcb8050}{ISPR}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00469\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[16U];}
\DoxyCodeLine{00470\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa056e3f59e88845ee47db4a43635b3a2}{ICPR}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00471\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[16U];}
\DoxyCodeLine{00472\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6e42ca3d9a1e12e75463cef68785d533}{IABR}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00473\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[16U];}
\DoxyCodeLine{00474\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4940c96f11d1c95d95a28e388f04d6d6}{ITNS}}[16U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00475\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[16U];}
\DoxyCodeLine{00476\ \ \ \_\_IOM\ uint8\_t\ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5db2c8af1dc93f6cb3a3929d325cd08c}{IPR}}[496U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00477\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED6[580U];}
\DoxyCodeLine{00478\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga37de89637466e007171c6b135299bc75}{STIR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00479\ \}\ \ \mbox{\hyperlink{struct_n_v_i_c___type}{NVIC\_Type}};}
\DoxyCodeLine{00480\ }
\DoxyCodeLine{00481\ \textcolor{comment}{/*\ Software\ Triggered\ Interrupt\ Register\ Definitions\ */}}
\DoxyCodeLine{00482\ \textcolor{preprocessor}{\#define\ NVIC\_STIR\_INTID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00483\ \textcolor{preprocessor}{\#define\ NVIC\_STIR\_INTID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ NVIC\_STIR\_INTID\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00484\ }
\DoxyCodeLine{00486\ }
\DoxyCodeLine{00487\ }
\DoxyCodeLine{00494\ }
\DoxyCodeLine{00498\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00499\ \{}
\DoxyCodeLine{00500\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga21e08d546d8b641bee298a459ea73e46}{CPUID}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00501\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0ca18ef984d132c6bf4d9b61cd00f05a}{ICSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00502\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga187a4578e920544ed967f98020fb8170}{VTOR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00503\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad3e5b8934c647eb1b7383c1894f01380}{AIRCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00504\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3a4840c6fa4d1ee75544f4032c88ec34}{SCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00505\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2d6653b0b70faac936046a02809b577f}{CCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00506\ \ \ \_\_IOM\ uint8\_t\ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9a442e7582573585ee0489267450dedb}{SHPR}}[12U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00507\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7b5ae9741a99808043394c4743b635c4}{SHCSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00508\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0cda9e061b42373383418663092ad19a}{CFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00509\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga14ad254659362b9752c69afe3fd80934}{HFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00510\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga191579bde0d21ff51d30a714fd887033}{DFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00511\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2d03d0b7cec2254f39eb1c46c7445e80}{MMFAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00512\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3f8e7e58be4e41c88dfa78f54589271c}{BFAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00513\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab65372404ce64b0f0b35e2709429404e}{AFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00514\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7a23d21186bc6aa71855a68666202984}{ID\_PFR}}[2U];\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00515\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gada1d3119c020983fdc949c2ccd406caa}{ID\_DFR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00516\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa5c5a6ccc7042927ce3feadc41872aa4}{ID\_ADR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00517\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad3ce108b65d07e91c4a1054d50e4bd8a}{ID\_MMFR}}[4U];\ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00518\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5be03d185d9bde32c5b9028f792f8e1e}{ID\_ISAR}}[6U];\ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00519\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad9899f5775251cf5ef0cb0845527afc2}{CLIDR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00520\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf3fe705fef8762763b6d61dbdf0ccc3d}{CTR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00521\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gafd063c9297a1a3b67e6d1d5e179e6a0e}{CCSIDR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00522\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad3884e8b6504ec63c1eaa8742e94df3d}{CSSELR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00523\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac6a860c1b8d8154a1f00d99d23b67764}{CPACR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00524\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga525790dfb9d9e3dd8eb126cdfebcd472}{NSACR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00525\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[92U];}
\DoxyCodeLine{00526\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad70825dd0869b7ccd07fb2b8680fcdb6}{STIR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00527\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[15U];}
\DoxyCodeLine{00528\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7a1ba0f875c0e97c1673882b1106e66b}{MVFR0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00529\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga75d6299150fdcbbcb765e22ff27c432e}{MVFR1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00530\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga280ef961518ecee3ed43a86404853c3d}{MVFR2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00531\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[1U];}
\DoxyCodeLine{00532\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga573260e7836dbc43707df97dd475a0c8}{ICIALLU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00533\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED6[1U];}
\DoxyCodeLine{00534\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5eca5a3e5aedd89a9655df8f5798e2b0}{ICIMVAU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00535\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4be79491ab1ed14f3b0237ba7e69063c}{DCIMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00536\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga22bcfd7e1bffebdbe98cdbc8d77a2f42}{DCISW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00537\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaae3caeea159ab54859ea11397f942cfa}{DCCMVAU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00538\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga042e3622c98de4e908cfda4f70d1f097}{DCCMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00539\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab95cc818be9fa7d25ae516f3fe6b7788}{DCCSW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00540\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4f59813582b53feb5f1afbbad3db2022}{DCCIMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00541\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf50f7a0a9574fe0e24a68bb4eca75140}{DCCISW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00542\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[6U];}
\DoxyCodeLine{00543\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaba8abbd3db06a07b50f56547501983f9}{ITCMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00544\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2836e932734240076ce91cf4484cdf43}{DTCMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00545\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0d53bcea294422b5b4ecfdcd9cdc1773}{AHBPCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00546\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga51f9bd107a4e1d46ba647384e5c825b5}{CACR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00547\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8c9d9eac30594dd061d34cfaacd5e4bb}{AHBSCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00548\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED8[1U];}
\DoxyCodeLine{00549\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga35a95c9a21f43a569a7ac212acb4cee7}{ABFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00550\ \}\ \mbox{\hyperlink{struct_s_c_b___type}{SCB\_Type}};}
\DoxyCodeLine{00551\ }
\DoxyCodeLine{00552\ \textcolor{comment}{/*\ SCB\ CPUID\ Register\ Definitions\ */}}
\DoxyCodeLine{00553\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_IMPLEMENTER\_Pos\ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00554\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_IMPLEMENTER\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CPUID\_IMPLEMENTER\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00555\ }
\DoxyCodeLine{00556\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_VARIANT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00557\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_VARIANT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CPUID\_VARIANT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00558\ }
\DoxyCodeLine{00559\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_ARCHITECTURE\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00560\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_ARCHITECTURE\_Msk\ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CPUID\_ARCHITECTURE\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00561\ }
\DoxyCodeLine{00562\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_PARTNO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00563\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_PARTNO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFUL\ <<\ SCB\_CPUID\_PARTNO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00564\ }
\DoxyCodeLine{00565\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_REVISION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00566\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_REVISION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCB\_CPUID\_REVISION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00567\ }
\DoxyCodeLine{00568\ \textcolor{comment}{/*\ SCB\ Interrupt\ Control\ State\ Register\ Definitions\ */}}
\DoxyCodeLine{00569\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDNMISET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00570\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDNMISET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDNMISET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00571\ }
\DoxyCodeLine{00572\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_NMIPENDSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ SCB\_ICSR\_PENDNMISET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00573\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_NMIPENDSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ SCB\_ICSR\_PENDNMISET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00574\ }
\DoxyCodeLine{00575\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDNMICLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00576\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDNMICLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDNMICLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00577\ }
\DoxyCodeLine{00578\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00579\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSVSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00580\ }
\DoxyCodeLine{00581\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00582\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSVCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00583\ }
\DoxyCodeLine{00584\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00585\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00586\ }
\DoxyCodeLine{00587\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00588\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00589\ }
\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_STTNS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00591\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_STTNS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_STTNS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00592\ }
\DoxyCodeLine{00593\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPREEMPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00595\ }
\DoxyCodeLine{00596\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00597\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00598\ }
\DoxyCodeLine{00599\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00600\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_ICSR\_VECTPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00601\ }
\DoxyCodeLine{00602\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00603\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_RETTOBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00604\ }
\DoxyCodeLine{00605\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00606\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ SCB\_ICSR\_VECTACTIVE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00607\ }
\DoxyCodeLine{00608\ \textcolor{comment}{/*\ SCB\ Vector\ Table\ Offset\ Register\ Definitions\ */}}
\DoxyCodeLine{00609\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00610\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFUL\ <<\ SCB\_VTOR\_TBLOFF\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00611\ }
\DoxyCodeLine{00612\ \textcolor{comment}{/*\ SCB\ Application\ Interrupt\ and\ Reset\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00613\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00614\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00615\ }
\DoxyCodeLine{00616\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00617\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEYSTAT\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00618\ }
\DoxyCodeLine{00619\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00620\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_ENDIANESS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00621\ }
\DoxyCodeLine{00622\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00623\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_PRIS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00624\ }
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_BFHFNMINS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00626\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_BFHFNMINS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_BFHFNMINS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00627\ }
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00629\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AIRCR\_PRIGROUP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00630\ }
\DoxyCodeLine{00631\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQS\_Pos\ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00632\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQS\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00633\ }
\DoxyCodeLine{00634\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00635\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00636\ }
\DoxyCodeLine{00637\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos\ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00638\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00639\ }
\DoxyCodeLine{00640\ \textcolor{comment}{/*\ SCB\ System\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00641\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00642\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SEVONPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00643\ }
\DoxyCodeLine{00644\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEPS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00645\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEPS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEPS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00646\ }
\DoxyCodeLine{00647\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00648\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00649\ }
\DoxyCodeLine{00650\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00651\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPONEXIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00652\ }
\DoxyCodeLine{00653\ \textcolor{comment}{/*\ SCB\ Configuration\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00654\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00655\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00656\ }
\DoxyCodeLine{00657\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_IC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00659\ }
\DoxyCodeLine{00660\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00661\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00662\ }
\DoxyCodeLine{00663\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKOFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00664\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKOFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_STKOFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00665\ }
\DoxyCodeLine{00666\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00667\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00668\ }
\DoxyCodeLine{00669\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00670\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DIV\_0\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00671\ }
\DoxyCodeLine{00672\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00673\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_UNALIGN\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00674\ }
\DoxyCodeLine{00675\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00676\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_USERSETMPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00677\ }
\DoxyCodeLine{00678\ \textcolor{comment}{/*\ SCB\ System\ Handler\ Control\ and\ State\ Register\ Definitions\ */}}
\DoxyCodeLine{00679\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTPENDED\_Pos\ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00680\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTPENDED\_Msk\ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_HARDFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00681\ }
\DoxyCodeLine{00682\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTPENDED\_Pos\ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00683\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTPENDED\_Msk\ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTPENDED\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00684\ }
\DoxyCodeLine{00685\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTENA\_Pos\ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00686\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTENA\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00687\ }
\DoxyCodeLine{00688\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00689\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00690\ }
\DoxyCodeLine{00691\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00692\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00693\ }
\DoxyCodeLine{00694\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00695\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00696\ }
\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Pos\ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00698\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00699\ }
\DoxyCodeLine{00700\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos\ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00701\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00702\ }
\DoxyCodeLine{00703\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos\ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00704\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00705\ }
\DoxyCodeLine{00706\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Pos\ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00707\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00708\ }
\DoxyCodeLine{00709\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00710\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SYSTICKACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00711\ }
\DoxyCodeLine{00712\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00713\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_PENDSVACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00714\ }
\DoxyCodeLine{00715\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00716\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MONITORACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00717\ }
\DoxyCodeLine{00718\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00719\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00720\ }
\DoxyCodeLine{00721\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_NMIACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00722\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_NMIACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_NMIACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00723\ }
\DoxyCodeLine{00724\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTACT\_Pos\ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00725\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTACT\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00726\ }
\DoxyCodeLine{00727\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00728\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00729\ }
\DoxyCodeLine{00730\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00731\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTACT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_HARDFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00732\ }
\DoxyCodeLine{00733\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00734\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00735\ }
\DoxyCodeLine{00736\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00737\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_SHCSR\_MEMFAULTACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00738\ }
\DoxyCodeLine{00739\ \textcolor{comment}{/*\ SCB\ Configurable\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00740\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00741\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_CFSR\_USGFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00742\ }
\DoxyCodeLine{00743\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00744\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CFSR\_BUSFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00745\ }
\DoxyCodeLine{00746\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00747\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_MEMFAULTSR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00748\ }
\DoxyCodeLine{00749\ \textcolor{comment}{/*\ MemManage\ Fault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00750\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00751\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MMARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00752\ }
\DoxyCodeLine{00753\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00754\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MLSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00755\ }
\DoxyCodeLine{00756\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00757\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00758\ }
\DoxyCodeLine{00759\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00760\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MUNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00761\ }
\DoxyCodeLine{00762\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00763\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DACCVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00764\ }
\DoxyCodeLine{00765\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00766\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_IACCVIOL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00767\ }
\DoxyCodeLine{00768\ \textcolor{comment}{/*\ BusFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00769\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00770\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_BFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00771\ }
\DoxyCodeLine{00772\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00773\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00774\ }
\DoxyCodeLine{00775\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00776\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00777\ }
\DoxyCodeLine{00778\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00779\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00780\ }
\DoxyCodeLine{00781\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00782\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IMPRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00783\ }
\DoxyCodeLine{00784\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00785\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_PRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00786\ }
\DoxyCodeLine{00787\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00788\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IBUSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00789\ }
\DoxyCodeLine{00790\ \textcolor{comment}{/*\ UsageFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00791\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 9U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00792\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DIVBYZERO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00793\ }
\DoxyCodeLine{00794\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00795\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNALIGNED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00796\ }
\DoxyCodeLine{00797\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKOF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00798\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKOF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKOF\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00799\ }
\DoxyCodeLine{00800\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00801\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_NOCP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00802\ }
\DoxyCodeLine{00803\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00804\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVPC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00805\ }
\DoxyCodeLine{00806\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00807\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVSTATE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00808\ }
\DoxyCodeLine{00809\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Pos\ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00810\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNDEFINSTR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00811\ }
\DoxyCodeLine{00812\ \textcolor{comment}{/*\ SCB\ Hard\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00813\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00814\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_DEBUGEVT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00815\ }
\DoxyCodeLine{00816\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00817\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_FORCED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00818\ }
\DoxyCodeLine{00819\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00820\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_VECTTBL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00821\ }
\DoxyCodeLine{00822\ \textcolor{comment}{/*\ SCB\ Debug\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00823\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00824\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_EXTERNAL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00825\ }
\DoxyCodeLine{00826\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00827\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_VCATCH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00828\ }
\DoxyCodeLine{00829\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00830\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_DWTTRAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00831\ }
\DoxyCodeLine{00832\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00833\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_BKPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00834\ }
\DoxyCodeLine{00835\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00836\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_DFSR\_HALTED\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00837\ }
\DoxyCodeLine{00838\ \textcolor{comment}{/*\ SCB\ Non-\/Secure\ Access\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00839\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP11\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00840\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP11\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_NSACR\_CP11\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00841\ }
\DoxyCodeLine{00842\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP10\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00843\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP10\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_NSACR\_CP10\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00844\ }
\DoxyCodeLine{00845\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CPn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00846\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CPn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_NSACR\_CPn\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00847\ }
\DoxyCodeLine{00848\ \textcolor{comment}{/*\ SCB\ Cache\ Level\ ID\ Register\ Definitions\ */}}
\DoxyCodeLine{00849\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00850\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOUU\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00851\ }
\DoxyCodeLine{00852\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00853\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00854\ }
\DoxyCodeLine{00855\ \textcolor{comment}{/*\ SCB\ Cache\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{00856\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00857\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CTR\_FORMAT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00858\ }
\DoxyCodeLine{00859\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00860\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_CWG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00861\ }
\DoxyCodeLine{00862\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_ERG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00863\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_ERG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_ERG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00864\ }
\DoxyCodeLine{00865\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_DMINLINE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00866\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_DMINLINE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_DMINLINE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00867\ }
\DoxyCodeLine{00868\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_IMINLINE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00869\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_IMINLINE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCB\_CTR\_IMINLINE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00870\ }
\DoxyCodeLine{00871\ \textcolor{comment}{/*\ SCB\ Cache\ Size\ ID\ Register\ Definitions\ */}}
\DoxyCodeLine{00872\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00873\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00874\ }
\DoxyCodeLine{00875\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WB\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00876\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WB\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WB\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00877\ }
\DoxyCodeLine{00878\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_RA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00879\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_RA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_RA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00880\ }
\DoxyCodeLine{00881\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00882\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00883\ }
\DoxyCodeLine{00884\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_NUMSETS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00885\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_NUMSETS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFUL\ <<\ SCB\_CCSIDR\_NUMSETS\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00886\ }
\DoxyCodeLine{00887\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_ASSOCIATIVITY\_Pos\ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00888\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_ASSOCIATIVITY\_Msk\ \ \ \ \ \ \ (0x3FFUL\ <<\ SCB\_CCSIDR\_ASSOCIATIVITY\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00889\ }
\DoxyCodeLine{00890\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_LINESIZE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00891\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_LINESIZE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (7UL\ }\textcolor{comment}{/*<<\ SCB\_CCSIDR\_LINESIZE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00892\ }
\DoxyCodeLine{00893\ \textcolor{comment}{/*\ SCB\ Cache\ Size\ Selection\ Register\ Definitions\ */}}
\DoxyCodeLine{00894\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_LEVEL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00895\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_LEVEL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CSSELR\_LEVEL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00896\ }
\DoxyCodeLine{00897\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_IND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00898\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_IND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CSSELR\_IND\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00899\ }
\DoxyCodeLine{00900\ \textcolor{comment}{/*\ SCB\ Software\ Triggered\ Interrupt\ Register\ Definitions\ */}}
\DoxyCodeLine{00901\ \textcolor{preprocessor}{\#define\ SCB\_STIR\_INTID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00902\ \textcolor{preprocessor}{\#define\ SCB\_STIR\_INTID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ SCB\_STIR\_INTID\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00903\ }
\DoxyCodeLine{00904\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Invalidate\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00905\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00906\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCISW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00907\ }
\DoxyCodeLine{00908\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00909\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCISW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00910\ }
\DoxyCodeLine{00911\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Clean\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00912\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00913\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCCSW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00914\ }
\DoxyCodeLine{00915\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00916\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCCSW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00917\ }
\DoxyCodeLine{00918\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Clean\ and\ Invalidate\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00919\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00920\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCCISW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00921\ }
\DoxyCodeLine{00922\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00923\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCCISW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00924\ }
\DoxyCodeLine{00925\ \textcolor{comment}{/*\ Instruction\ Tightly-\/Coupled\ Memory\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00926\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00927\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_ITCMCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00928\ }
\DoxyCodeLine{00929\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RETEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00930\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RETEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ITCMCR\_RETEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00931\ }
\DoxyCodeLine{00932\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RMW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00933\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RMW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ITCMCR\_RMW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00934\ }
\DoxyCodeLine{00935\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00936\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_ITCMCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00937\ }
\DoxyCodeLine{00938\ \textcolor{comment}{/*\ Data\ Tightly-\/Coupled\ Memory\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00939\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00940\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_DTCMCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00941\ }
\DoxyCodeLine{00942\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RETEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00943\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RETEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DTCMCR\_RETEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00944\ }
\DoxyCodeLine{00945\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RMW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00946\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RMW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DTCMCR\_RMW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00947\ }
\DoxyCodeLine{00948\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00949\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_DTCMCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00950\ }
\DoxyCodeLine{00951\ \textcolor{comment}{/*\ AHBP\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00952\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00953\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AHBPCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00954\ }
\DoxyCodeLine{00955\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00956\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_AHBPCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00957\ }
\DoxyCodeLine{00958\ \textcolor{comment}{/*\ L1\ Cache\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00959\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_FORCEWT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00960\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_FORCEWT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CACR\_FORCEWT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00961\ }
\DoxyCodeLine{00962\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_ECCEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00963\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_ECCEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CACR\_ECCEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00964\ }
\DoxyCodeLine{00965\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_SIWT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00966\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_SIWT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CACR\_SIWT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00967\ }
\DoxyCodeLine{00968\ \textcolor{comment}{/*\ AHBS\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00969\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_INITCOUNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00970\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_INITCOUNT\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ SCB\_AHBPCR\_INITCOUNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00971\ }
\DoxyCodeLine{00972\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_TPRI\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00973\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_TPRI\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_AHBPCR\_TPRI\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00974\ }
\DoxyCodeLine{00975\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_CTL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00976\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_CTL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ }\textcolor{comment}{/*<<\ SCB\_AHBPCR\_CTL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00977\ }
\DoxyCodeLine{00978\ \textcolor{comment}{/*\ Auxiliary\ Bus\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00979\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIMTYPE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00980\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIMTYPE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_ABFSR\_AXIMTYPE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00981\ }
\DoxyCodeLine{00982\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_EPPB\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00983\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_EPPB\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_EPPB\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00984\ }
\DoxyCodeLine{00985\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00986\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_AXIM\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00987\ }
\DoxyCodeLine{00988\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AHBP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00989\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AHBP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_AHBP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00990\ }
\DoxyCodeLine{00991\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_DTCM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00992\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_DTCM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_DTCM\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00993\ }
\DoxyCodeLine{00994\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_ITCM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00995\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_ITCM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_ABFSR\_ITCM\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00996\ }
\DoxyCodeLine{00998\ }
\DoxyCodeLine{00999\ }
\DoxyCodeLine{01006\ }
\DoxyCodeLine{01010\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01011\ \{}
\DoxyCodeLine{01012\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01013\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga34ec1d771245eb9bd0e3ec9336949762}{ICTR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01014\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga13af9b718dde7481f1c0344f00593c23}{ACTLR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01015\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga356efebfcbdaecaf1176e6cd86a60bf1}{CPPWR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01016\ \}\ \mbox{\hyperlink{struct_s_cn_s_c_b___type}{SCnSCB\_Type}};}
\DoxyCodeLine{01017\ }
\DoxyCodeLine{01018\ \textcolor{comment}{/*\ Interrupt\ Controller\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01019\ \textcolor{preprocessor}{\#define\ SCnSCB\_ICTR\_INTLINESNUM\_Pos\ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01020\ \textcolor{preprocessor}{\#define\ SCnSCB\_ICTR\_INTLINESNUM\_Msk\ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCnSCB\_ICTR\_INTLINESNUM\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01021\ }
\DoxyCodeLine{01023\ }
\DoxyCodeLine{01024\ }
\DoxyCodeLine{01031\ }
\DoxyCodeLine{01035\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01036\ \{}
\DoxyCodeLine{01037\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga875e7afa5c4fd43997fb544a4ac6e37e}{CTRL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01038\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4780a489256bb9f54d0ba8ed4de191cd}{LOAD}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01039\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9b5420d17e8e43104ddd4ae5a610af93}{VAL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01040\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gafcadb0c6d35b21cdc0018658a13942de}{CALIB}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01041\ \}\ \mbox{\hyperlink{struct_sys_tick___type}{SysTick\_Type}};}
\DoxyCodeLine{01042\ }
\DoxyCodeLine{01043\ \textcolor{comment}{/*\ SysTick\ Control\ /\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01044\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_COUNTFLAG\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01045\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_COUNTFLAG\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_COUNTFLAG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01046\ }
\DoxyCodeLine{01047\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_CLKSOURCE\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01048\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_CLKSOURCE\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_CLKSOURCE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01049\ }
\DoxyCodeLine{01050\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_TICKINT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01051\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_TICKINT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_TICKINT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01052\ }
\DoxyCodeLine{01053\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01054\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SysTick\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01055\ }
\DoxyCodeLine{01056\ \textcolor{comment}{/*\ SysTick\ Reload\ Register\ Definitions\ */}}
\DoxyCodeLine{01057\ \textcolor{preprocessor}{\#define\ SysTick\_LOAD\_RELOAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01058\ \textcolor{preprocessor}{\#define\ SysTick\_LOAD\_RELOAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_LOAD\_RELOAD\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01059\ }
\DoxyCodeLine{01060\ \textcolor{comment}{/*\ SysTick\ Current\ Register\ Definitions\ */}}
\DoxyCodeLine{01061\ \textcolor{preprocessor}{\#define\ SysTick\_VAL\_CURRENT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01062\ \textcolor{preprocessor}{\#define\ SysTick\_VAL\_CURRENT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_VAL\_CURRENT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01063\ }
\DoxyCodeLine{01064\ \textcolor{comment}{/*\ SysTick\ Calibration\ Register\ Definitions\ */}}
\DoxyCodeLine{01065\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_NOREF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01066\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_NOREF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CALIB\_NOREF\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01067\ }
\DoxyCodeLine{01068\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_SKEW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01069\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_SKEW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CALIB\_SKEW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01070\ }
\DoxyCodeLine{01071\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_TENMS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01072\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_TENMS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_CALIB\_TENMS\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01073\ }
\DoxyCodeLine{01075\ }
\DoxyCodeLine{01076\ }
\DoxyCodeLine{01083\ }
\DoxyCodeLine{01087\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01088\ \{}
\DoxyCodeLine{01089\ \ \ \_\_OM\ \ \textcolor{keyword}{union}}
\DoxyCodeLine{01090\ \ \ \{}
\DoxyCodeLine{01091\ \ \ \ \ \_\_OM\ \ uint8\_t\ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae773bf9f9dac64e6c28b14aa39f74275}{u8}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01092\ \ \ \ \ \_\_OM\ \ uint16\_t\ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga962a970dfd286cad7f8a8577e87d4ad3}{u16}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01093\ \ \ \ \ \_\_OM\ \ uint32\_t\ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5834885903a557674f078f3b71fa8bc8}{u32}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01094\ \ \ \}\ \ PORT\ [32U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01095\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[864U];}
\DoxyCodeLine{01096\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gacd03c6858f7b678dab6a6121462e7807}{TER}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01097\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[15U];}
\DoxyCodeLine{01098\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae907229ba50538bf370fbdfd54c099a2}{TPR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01099\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[15U];}
\DoxyCodeLine{01100\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga04b9fbc83759cb818dfa161d39628426}{TCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01101\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[29U];}
\DoxyCodeLine{01102\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa9da04891e48d1a2f054de186e9c4c94}{IWR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01103\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga66eb82a070953f09909f39b8e516fb91}{IRR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01104\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae2ce4d3a54df2fd11a197ccac4406cd0}{IMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01105\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[43U];}
\DoxyCodeLine{01106\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7f9c2a2113a11c7f3e98915f95b669d5}{LAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01107\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3861c67933a24dd6632288c4ed0b80c8}{LSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01108\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[1U];}
\DoxyCodeLine{01109\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2372a4ebb63e36d1eb3fcf83a74fd537}{DEVARCH}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01110\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED6[4U];}
\DoxyCodeLine{01111\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaad5e11dd4baf6d941bd6c7450f60a158}{PID4}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01112\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf9085648bf18f69b5f9d1136d45e1d37}{PID5}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01113\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad34dbe6b1072c77d36281049c8b169f6}{PID6}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01114\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2bcec6803f28f30d5baf5e20e3517d3d}{PID7}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01115\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab4a4cc97ad658e9c46cf17490daffb8a}{PID0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01116\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga89ea1d805a668d6589b22d8e678eb6a4}{PID1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01117\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8471c4d77b7107cf580587509da69f38}{PID2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01118\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf317d5e2d946d70e6fb67c02b92cc8a3}{PID3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01119\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga30bb2b166b1723867da4a708935677ba}{CID0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01120\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac40df2c3a6cef02f90b4e82c8204756f}{CID1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01121\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8000b92e4e528ae7ac4cb8b8d9f6757d}{CID2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01122\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga43451f43f514108d9eaed5b017f8d921}{CID3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01123\ \}\ \mbox{\hyperlink{struct_i_t_m___type}{ITM\_Type}};}
\DoxyCodeLine{01124\ }
\DoxyCodeLine{01125\ \textcolor{comment}{/*\ ITM\ Stimulus\ Port\ Register\ Definitions\ */}}
\DoxyCodeLine{01126\ \textcolor{preprocessor}{\#define\ ITM\_STIM\_DISABLED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01127\ \textcolor{preprocessor}{\#define\ ITM\_STIM\_DISABLED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ ITM\_STIM\_DISABLED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01128\ }
\DoxyCodeLine{01129\ \textcolor{preprocessor}{\#define\ ITM\_STIM\_FIFOREADY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01130\ \textcolor{preprocessor}{\#define\ ITM\_STIM\_FIFOREADY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ ITM\_STIM\_FIFOREADY\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01131\ }
\DoxyCodeLine{01132\ \textcolor{comment}{/*\ ITM\ Trace\ Privilege\ Register\ Definitions\ */}}
\DoxyCodeLine{01133\ \textcolor{preprocessor}{\#define\ ITM\_TPR\_PRIVMASK\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01134\ \textcolor{preprocessor}{\#define\ ITM\_TPR\_PRIVMASK\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ ITM\_TPR\_PRIVMASK\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01135\ }
\DoxyCodeLine{01136\ \textcolor{comment}{/*\ ITM\ Trace\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01137\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_BUSY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01138\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_BUSY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_BUSY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01139\ }
\DoxyCodeLine{01140\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TRACEBUSID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01141\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TRACEBUSID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FUL\ <<\ ITM\_TCR\_TRACEBUSID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01142\ }
\DoxyCodeLine{01143\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_GTSFREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01144\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_GTSFREQ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ ITM\_TCR\_GTSFREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01145\ }
\DoxyCodeLine{01146\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSPRESCALE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01147\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSPRESCALE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ ITM\_TCR\_TSPRESCALE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01148\ }
\DoxyCodeLine{01149\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_STALLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01150\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_STALLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_STALLENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01151\ }
\DoxyCodeLine{01152\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SWOENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01153\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SWOENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_SWOENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01154\ }
\DoxyCodeLine{01155\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_DWTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01156\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_DWTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_DWTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01157\ }
\DoxyCodeLine{01158\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SYNCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01159\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SYNCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_SYNCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01160\ }
\DoxyCodeLine{01161\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01162\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_TSENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01163\ }
\DoxyCodeLine{01164\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_ITMENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01165\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_ITMENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_TCR\_ITMENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01166\ }
\DoxyCodeLine{01167\ \textcolor{comment}{/*\ ITM\ Integration\ Write\ Register\ Definitions\ */}}
\DoxyCodeLine{01168\ \textcolor{preprocessor}{\#define\ ITM\_IWR\_ATVALIDM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01169\ \textcolor{preprocessor}{\#define\ ITM\_IWR\_ATVALIDM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_IWR\_ATVALIDM\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01170\ }
\DoxyCodeLine{01171\ \textcolor{comment}{/*\ ITM\ Integration\ Read\ Register\ Definitions\ */}}
\DoxyCodeLine{01172\ \textcolor{preprocessor}{\#define\ ITM\_IRR\_ATREADYM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01173\ \textcolor{preprocessor}{\#define\ ITM\_IRR\_ATREADYM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_IRR\_ATREADYM\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01174\ }
\DoxyCodeLine{01175\ \textcolor{comment}{/*\ ITM\ Integration\ Mode\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01176\ \textcolor{preprocessor}{\#define\ ITM\_IMCR\_INTEGRATION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01177\ \textcolor{preprocessor}{\#define\ ITM\_IMCR\_INTEGRATION\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_IMCR\_INTEGRATION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01178\ }
\DoxyCodeLine{01179\ \textcolor{comment}{/*\ ITM\ Lock\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01180\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_ByteAcc\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01181\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_ByteAcc\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_LSR\_ByteAcc\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01182\ }
\DoxyCodeLine{01183\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Access\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01184\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Access\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_LSR\_Access\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01185\ }
\DoxyCodeLine{01186\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Present\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01187\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Present\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_LSR\_Present\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01188\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_ITM\ */}}
\DoxyCodeLine{01190\ }
\DoxyCodeLine{01191\ }
\DoxyCodeLine{01198\ }
\DoxyCodeLine{01202\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01203\ \{}
\DoxyCodeLine{01204\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadd790c53410023b3b581919bb681fe2a}{CTRL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01205\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga102eaa529d9098242851cb57c52b42d9}{CYCCNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01206\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2c08096c82abe245c0fa97badc458154}{CPICNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01207\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9fe20c16c5167ca61486caf6832686d1}{EXCCNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01208\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga416a54e2084ce66e5ca74f152a5ecc70}{SLEEPCNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01209\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gacc05d89bdb1b4fe2fa499920ec02d0b1}{LSUCNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01210\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga1cfc48384ebd8fd8fb7e5d955aae6c97}{FOLDCNT}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01211\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6353ca1d1ad9bc1be05d3b5632960113}{PCSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01212\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga61c2965af5bc0643f9af65620b0e67c9}{COMP0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01213\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[1U];}
\DoxyCodeLine{01214\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga579ae082f58a0317b7ef029b20f52889}{FUNCTION0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01215\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[1U];}
\DoxyCodeLine{01216\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga38714af6b7fa7c64d68f5e1efbe7a931}{COMP1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01217\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[1U];}
\DoxyCodeLine{01218\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8dfcf25675f9606aa305c46e85182e4e}{FUNCTION1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01219\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01220\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5ae6dde39989f27bae90afc2347deb46}{COMP2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01221\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[1U];}
\DoxyCodeLine{01222\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab1b60d6600c38abae515bab8e86a188f}{FUNCTION2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01223\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED6[1U];}
\DoxyCodeLine{01224\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga85eb73d1848ac3f82d39d6c3e8910847}{COMP3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01225\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[1U];}
\DoxyCodeLine{01226\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga52d4ff278fae6f9216c63b74ce328841}{FUNCTION3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01227\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED8[1U];}
\DoxyCodeLine{01228\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga86bc7f4ad425a05b29978a6f97563783}{COMP4}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01229\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED9[1U];}
\DoxyCodeLine{01230\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2fa7fd33c3fae711e0d0e683f29b5b6d}{FUNCTION4}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01231\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED10[1U];}
\DoxyCodeLine{01232\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga07667ec9dd833ecab52bf2cf802d9acb}{COMP5}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01233\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED11[1U];}
\DoxyCodeLine{01234\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2f33ef0ce606e4850ecde8d044f7bb5b}{FUNCTION5}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01235\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED12[1U];}
\DoxyCodeLine{01236\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga1256ac92acb94add255ff31aca31070d}{COMP6}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01237\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED13[1U];}
\DoxyCodeLine{01238\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa8f49a707a5d85cf554b9bef54c19380}{FUNCTION6}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01239\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED14[1U];}
\DoxyCodeLine{01240\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga46db6f5289d840f0b9886ae598352452}{COMP7}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01241\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED15[1U];}
\DoxyCodeLine{01242\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gababf5d870650c4a480302b65bdb66741}{FUNCTION7}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01243\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED16[1U];}
\DoxyCodeLine{01244\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaee138bc70746585e4ccf62557954c07f}{COMP8}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01245\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED17[1U];}
\DoxyCodeLine{01246\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gacdd6b87ea4bc95345687074c53098e75}{FUNCTION8}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01247\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED18[1U];}
\DoxyCodeLine{01248\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gabf79b853fc2d25de9c03bdb183e4aee0}{COMP9}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01249\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED19[1U];}
\DoxyCodeLine{01250\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga379b5b8f7d40003b7bdabd535e0378a1}{FUNCTION9}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01251\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED20[1U];}
\DoxyCodeLine{01252\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gacf26842434e5cd1487a49812ec842d03}{COMP10}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01253\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED21[1U];}
\DoxyCodeLine{01254\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga63c72c28fd46b22230894366a8d9cdda}{FUNCTION10}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01255\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED22[1U];}
\DoxyCodeLine{01256\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa199b91c854edd21ded38b8922d1e2a7}{COMP11}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01257\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED23[1U];}
\DoxyCodeLine{01258\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga214f7478184150e43175c05aecad6c96}{FUNCTION11}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01259\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED24[1U];}
\DoxyCodeLine{01260\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9115fd187d8cbcb9d6ec5eba938b81ea}{COMP12}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01261\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED25[1U];}
\DoxyCodeLine{01262\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga521771b3dfe2ea48463e1e91d01448b6}{FUNCTION12}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01263\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED26[1U];}
\DoxyCodeLine{01264\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gabc29ac14df61ec3f8f3d28ca92892d8a}{COMP13}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01265\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED27[1U];}
\DoxyCodeLine{01266\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf9ea0b56769614c5c5699003b3df39f0}{FUNCTION13}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01267\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED28[1U];}
\DoxyCodeLine{01268\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga85368a4ec78f4074e5f9cbba92ae1eb9}{COMP14}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01269\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED29[1U];}
\DoxyCodeLine{01270\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga85138a411459f923ea8e05312d70af71}{FUNCTION14}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01271\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED30[1U];}
\DoxyCodeLine{01272\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa46b44e5aacd3ca3937741f423ab480f}{COMP15}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01273\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED31[1U];}
\DoxyCodeLine{01274\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6e5fda09de44dfcd3e177c16028ceb74}{FUNCTION15}};\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01275\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED32[934U];}
\DoxyCodeLine{01276\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4281befcc19ee69afdd50801cb1c9bcf}{LSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01277\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED33[1U];}
\DoxyCodeLine{01278\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae60dbff3143d15cd04ac984084d8fbc7}{DEVARCH}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01279\ \}\ \mbox{\hyperlink{struct_d_w_t___type}{DWT\_Type}};}
\DoxyCodeLine{01280\ }
\DoxyCodeLine{01281\ \textcolor{comment}{/*\ DWT\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01282\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01283\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_NUMCOMP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01284\ }
\DoxyCodeLine{01285\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01286\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOTRCPKT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01287\ }
\DoxyCodeLine{01288\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01289\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOEXTTRIG\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01290\ }
\DoxyCodeLine{01291\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01292\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOCYCCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01293\ }
\DoxyCodeLine{01294\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01295\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOPRFCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01296\ }
\DoxyCodeLine{01297\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCDISS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01298\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCDISS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCDISS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01299\ }
\DoxyCodeLine{01300\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01301\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01302\ }
\DoxyCodeLine{01303\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01304\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_FOLDEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01305\ }
\DoxyCodeLine{01306\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01307\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_LSUEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01308\ }
\DoxyCodeLine{01309\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01310\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_SLEEPEVTENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01311\ }
\DoxyCodeLine{01312\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01313\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01314\ }
\DoxyCodeLine{01315\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01316\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CPIEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01317\ }
\DoxyCodeLine{01318\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01319\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCTRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01320\ }
\DoxyCodeLine{01321\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01322\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_PCSAMPLENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01323\ }
\DoxyCodeLine{01324\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01325\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_CTRL\_SYNCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01326\ }
\DoxyCodeLine{01327\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01328\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01329\ }
\DoxyCodeLine{01330\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01331\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTINIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01332\ }
\DoxyCodeLine{01333\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01334\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTPRESET\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01335\ }
\DoxyCodeLine{01336\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01337\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ DWT\_CTRL\_CYCCNTENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01338\ }
\DoxyCodeLine{01339\ \textcolor{comment}{/*\ DWT\ CPI\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01340\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01341\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_CPICNT\_CPICNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01342\ }
\DoxyCodeLine{01343\ \textcolor{comment}{/*\ DWT\ Exception\ Overhead\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01344\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01345\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_EXCCNT\_EXCCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01346\ }
\DoxyCodeLine{01347\ \textcolor{comment}{/*\ DWT\ Sleep\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01348\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01349\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01350\ }
\DoxyCodeLine{01351\ \textcolor{comment}{/*\ DWT\ LSU\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01352\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01353\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_LSUCNT\_LSUCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01354\ }
\DoxyCodeLine{01355\ \textcolor{comment}{/*\ DWT\ Folded-\/instruction\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01356\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01357\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_FOLDCNT\_FOLDCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01358\ }
\DoxyCodeLine{01359\ \textcolor{comment}{/*\ DWT\ Comparator\ Function\ Register\ Definitions\ */}}
\DoxyCodeLine{01360\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01361\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ DWT\_FUNCTION\_ID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01362\ }
\DoxyCodeLine{01363\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Pos\ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01364\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_MATCHED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01365\ }
\DoxyCodeLine{01366\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01367\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Msk\ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_FUNCTION\_DATAVSIZE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01368\ }
\DoxyCodeLine{01369\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ACTION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01370\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ACTION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_ACTION\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01371\ }
\DoxyCodeLine{01372\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01373\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ DWT\_FUNCTION\_MATCH\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01374\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_DWT\ */}}
\DoxyCodeLine{01376\ }
\DoxyCodeLine{01377\ }
\DoxyCodeLine{01384\ }
\DoxyCodeLine{01388\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01389\ \{}
\DoxyCodeLine{01390\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga037901d7cb870199ac51d9ad0ef9fd1a}{SSPSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01391\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8826aa84e5806053395a742d38d59d0f}{CSPSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01392\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[2U];}
\DoxyCodeLine{01393\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9e5e4421ef9c3d5b7ff8b24abd4e99b3}{ACPR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01394\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[55U];}
\DoxyCodeLine{01395\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12f79d4e3ddc69893ba8bff890d04cc5}{SPPR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01396\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[131U];}
\DoxyCodeLine{01397\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6c47a0b4c7ffc66093ef993d36bb441c}{FFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01398\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3f68b6e73561b4849ebf953a894df8d2}{FFCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01399\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad6901bfd8a0089ca7e8a20475cf494a8}{FSCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01400\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[759U];}
\DoxyCodeLine{01401\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4d4cd2357f72333a82a1313228287bbd}{TRIGGER}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01402\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa4d7b5cf39dff9f53bf7f69bc287a814}{FIFO0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01403\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab358319b969d3fed0f89bbe33e9f1652}{ITATBCTR2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01404\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01405\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaaa573b2e073e76e93c51ecec79c616d0}{ITATBCTR0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01406\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga061372fcd72f1eea871e2d9c1be849bc}{FIFO1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01407\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaaa4c823c10f115f7517c82ef86a5a68d}{ITCTRL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01408\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[39U];}
\DoxyCodeLine{01409\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf8b7d15fa5252b733dd4b11fa1b5730a}{CLAIMSET}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01410\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0e10e292cb019a832b03ddd055b2f6ac}{CLAIMCLR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01411\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[8U];}
\DoxyCodeLine{01412\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gabc0ecda8a5446bc754080276bad77514}{DEVID}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01413\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad98855854a719bbea33061e71529a472}{DEVTYPE}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01414\ \}\ \mbox{\hyperlink{struct_t_p_i___type}{TPI\_Type}};}
\DoxyCodeLine{01415\ }
\DoxyCodeLine{01416\ \textcolor{comment}{/*\ TPI\ Asynchronous\ Clock\ Prescaler\ Register\ Definitions\ */}}
\DoxyCodeLine{01417\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01418\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFUL\ }\textcolor{comment}{/*<<\ TPI\_ACPR\_PRESCALER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01419\ }
\DoxyCodeLine{01420\ \textcolor{comment}{/*\ TPI\ Selected\ Pin\ Protocol\ Register\ Definitions\ */}}
\DoxyCodeLine{01421\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01422\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ }\textcolor{comment}{/*<<\ TPI\_SPPR\_TXMODE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01423\ }
\DoxyCodeLine{01424\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01425\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01426\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtNonStop\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01427\ }
\DoxyCodeLine{01428\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01429\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_TCPresent\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01430\ }
\DoxyCodeLine{01431\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01432\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtStopped\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01433\ }
\DoxyCodeLine{01434\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01435\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_FFSR\_FlInProg\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01436\ }
\DoxyCodeLine{01437\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01438\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01439\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_TrigIn\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01440\ }
\DoxyCodeLine{01441\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01442\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_EnFCont\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01443\ }
\DoxyCodeLine{01444\ \textcolor{comment}{/*\ TPI\ TRIGGER\ Register\ Definitions\ */}}
\DoxyCodeLine{01445\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01446\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_TRIGGER\_TRIGGER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01447\ }
\DoxyCodeLine{01448\ \textcolor{comment}{/*\ TPI\ Integration\ ETM\ Data\ Register\ Definitions\ (FIFO0)\ */}}
\DoxyCodeLine{01449\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01450\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01451\ }
\DoxyCodeLine{01452\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01453\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01454\ }
\DoxyCodeLine{01455\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01456\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01457\ }
\DoxyCodeLine{01458\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01459\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01460\ }
\DoxyCodeLine{01461\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01462\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01463\ }
\DoxyCodeLine{01464\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01465\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01466\ }
\DoxyCodeLine{01467\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01468\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ TPI\_FIFO0\_ETM0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01469\ }
\DoxyCodeLine{01470\ \textcolor{comment}{/*\ TPI\ ITATBCTR2\ Register\ Definitions\ */}}
\DoxyCodeLine{01471\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01472\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR2\_ATREADY\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01473\ }
\DoxyCodeLine{01474\ \textcolor{comment}{/*\ TPI\ Integration\ ITM\ Data\ Register\ Definitions\ (FIFO1)\ */}}
\DoxyCodeLine{01475\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01476\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01477\ }
\DoxyCodeLine{01478\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01479\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01480\ }
\DoxyCodeLine{01481\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01482\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01483\ }
\DoxyCodeLine{01484\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01485\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01486\ }
\DoxyCodeLine{01487\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01488\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO1\_ITM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01489\ }
\DoxyCodeLine{01490\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01491\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO1\_ITM1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01492\ }
\DoxyCodeLine{01493\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01494\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ TPI\_FIFO1\_ITM0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01495\ }
\DoxyCodeLine{01496\ \textcolor{comment}{/*\ TPI\ ITATBCTR0\ Register\ Definitions\ */}}
\DoxyCodeLine{01497\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01498\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR0\_ATREADY\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01499\ }
\DoxyCodeLine{01500\ \textcolor{comment}{/*\ TPI\ Integration\ Mode\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01501\ \textcolor{preprocessor}{\#define\ TPI\_ITCTRL\_Mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01502\ \textcolor{preprocessor}{\#define\ TPI\_ITCTRL\_Mode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITCTRL\_Mode\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01503\ }
\DoxyCodeLine{01504\ \textcolor{comment}{/*\ TPI\ DEVID\ Register\ Definitions\ */}}
\DoxyCodeLine{01505\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NRZVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01506\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NRZVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_NRZVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01507\ }
\DoxyCodeLine{01508\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01509\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_MANCVALID\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01510\ }
\DoxyCodeLine{01511\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_PTINVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01512\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_PTINVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_PTINVALID\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01513\ }
\DoxyCodeLine{01514\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01515\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ TPI\_DEVID\_MinBufSz\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01516\ }
\DoxyCodeLine{01517\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_AsynClkIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01518\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_AsynClkIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_AsynClkIn\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01519\ }
\DoxyCodeLine{01520\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01521\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ TPI\_DEVID\_NrTraceInput\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01522\ }
\DoxyCodeLine{01523\ \textcolor{comment}{/*\ TPI\ DEVTYPE\ Register\ Definitions\ */}}
\DoxyCodeLine{01524\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Pos\ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01525\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ TPI\_DEVTYPE\_MajorType\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01526\ }
\DoxyCodeLine{01527\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01528\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ TPI\_DEVTYPE\_SubType\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01529\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_TPI\ */}}
\DoxyCodeLine{01531\ }
\DoxyCodeLine{01532\ }
\DoxyCodeLine{01533\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01540\ }
\DoxyCodeLine{01544\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01545\ \{}
\DoxyCodeLine{01546\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0433efc1383674bc8e86cc0e830b462d}{TYPE}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01547\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4d81d6aa73a9287bafba2bcc5ffc6d18}{CTRL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01548\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa800d44f4d3520cc891d7b8d711320c1}{RNR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01549\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac953770d38a7d322b971d93eb8a5b062}{RBAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01550\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3e1c3c971bab068b1d4c689db3221b40}{RLAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01551\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga13d69b9bea12861383f3a62764b02f63}{RBAR\_A1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01552\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga290082b50ab1dd1649211adaa1801ee9}{RLAR\_A1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01553\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga57dc551614932150e684fcc60590c2c4}{RBAR\_A2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01554\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga983793154742e272a91dc54c4b453b4a}{RLAR\_A2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01555\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga345911aabecd1f7d93a1bff7738b0d86}{RBAR\_A3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01556\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga787a145b788c49d66c8b5e3350a291b7}{RLAR\_A3}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01557\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1];}
\DoxyCodeLine{01558\ \ \ \textcolor{keyword}{union\ }\{}
\DoxyCodeLine{01559\ \ \ \_\_IOM\ uint32\_t\ MAIR[2];}
\DoxyCodeLine{01560\ \ \ \textcolor{keyword}{struct\ }\{}
\DoxyCodeLine{01561\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3b47c220774ad7786bb42ea3622b0693}{MAIR0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01562\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac2840c137a056aeb543bd2d618992a03}{MAIR1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01563\ \ \ \};}
\DoxyCodeLine{01564\ \ \ \};}
\DoxyCodeLine{01565\ \}\ \mbox{\hyperlink{struct_m_p_u___type}{MPU\_Type}};}
\DoxyCodeLine{01566\ }
\DoxyCodeLine{01567\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_RALIASES\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U}}
\DoxyCodeLine{01568\ }
\DoxyCodeLine{01569\ \textcolor{comment}{/*\ MPU\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01570\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01571\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_IREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01572\ }
\DoxyCodeLine{01573\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01574\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_DREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01575\ }
\DoxyCodeLine{01576\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01577\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_TYPE\_SEPARATE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01578\ }
\DoxyCodeLine{01579\ \textcolor{comment}{/*\ MPU\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01580\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01581\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_PRIVDEFENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01582\ }
\DoxyCodeLine{01583\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01584\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_HFNMIENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01585\ }
\DoxyCodeLine{01586\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01587\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01588\ }
\DoxyCodeLine{01589\ \textcolor{comment}{/*\ MPU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01590\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01591\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01592\ }
\DoxyCodeLine{01593\ \textcolor{comment}{/*\ MPU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01594\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01595\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RBAR\_ADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01596\ }
\DoxyCodeLine{01597\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_SH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01598\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_SH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ MPU\_RBAR\_SH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01599\ }
\DoxyCodeLine{01600\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_AP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01601\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_AP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ MPU\_RBAR\_AP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01602\ }
\DoxyCodeLine{01603\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_XN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01604\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_XN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (01UL\ }\textcolor{comment}{/*<<\ MPU\_RBAR\_XN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01605\ }
\DoxyCodeLine{01606\ \textcolor{comment}{/*\ MPU\ Region\ Limit\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01607\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_LIMIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01608\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_LIMIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RLAR\_LIMIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01609\ }
\DoxyCodeLine{01610\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_PXN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01611\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_PXN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ MPU\_RLAR\_PXN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01612\ }
\DoxyCodeLine{01613\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_AttrIndx\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01614\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_AttrIndx\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RLAR\_AttrIndx\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01615\ }
\DoxyCodeLine{01616\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01617\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_RLAR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01618\ }
\DoxyCodeLine{01619\ \textcolor{comment}{/*\ MPU\ Memory\ Attribute\ Indirection\ Register\ 0\ Definitions\ */}}
\DoxyCodeLine{01620\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr3\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01621\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr3\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr3\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01622\ }
\DoxyCodeLine{01623\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01624\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01625\ }
\DoxyCodeLine{01626\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01627\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01628\ }
\DoxyCodeLine{01629\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01630\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_MAIR0\_Attr0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01631\ }
\DoxyCodeLine{01632\ \textcolor{comment}{/*\ MPU\ Memory\ Attribute\ Indirection\ Register\ 1\ Definitions\ */}}
\DoxyCodeLine{01633\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr7\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01634\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr7\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr7\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01635\ }
\DoxyCodeLine{01636\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr6\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01637\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr6\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr6\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01638\ }
\DoxyCodeLine{01639\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr5\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01640\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr5\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr5\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01641\ }
\DoxyCodeLine{01642\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr4\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01643\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr4\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_MAIR1\_Attr4\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01644\ }
\DoxyCodeLine{01646\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01647\ }
\DoxyCodeLine{01648\ }
\DoxyCodeLine{01649\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01656\ }
\DoxyCodeLine{01660\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01661\ \{}
\DoxyCodeLine{01662\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01663\ \ \ \_\_IM\ \ uint32\_t\ TYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01664\ \textcolor{preprocessor}{\#if\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01665\ \ \ \_\_IOM\ uint32\_t\ RNR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01666\ \ \ \_\_IOM\ uint32\_t\ RBAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01667\ \ \ \_\_IOM\ uint32\_t\ RLAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01668\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{01669\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[3];}
\DoxyCodeLine{01670\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01671\ \ \ \_\_IOM\ uint32\_t\ SFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01672\ \ \ \_\_IOM\ uint32\_t\ SFAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01673\ \}\ SAU\_Type;}
\DoxyCodeLine{01674\ }
\DoxyCodeLine{01675\ \textcolor{comment}{/*\ SAU\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01676\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ALLNS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01677\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ALLNS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_CTRL\_ALLNS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01678\ }
\DoxyCodeLine{01679\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01680\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SAU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01681\ }
\DoxyCodeLine{01682\ \textcolor{comment}{/*\ SAU\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01683\ \textcolor{preprocessor}{\#define\ SAU\_TYPE\_SREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01684\ \textcolor{preprocessor}{\#define\ SAU\_TYPE\_SREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SAU\_TYPE\_SREGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01685\ }
\DoxyCodeLine{01686\ \textcolor{preprocessor}{\#if\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01687\ \textcolor{comment}{/*\ SAU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01688\ \textcolor{preprocessor}{\#define\ SAU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01689\ \textcolor{preprocessor}{\#define\ SAU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SAU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01690\ }
\DoxyCodeLine{01691\ \textcolor{comment}{/*\ SAU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01692\ \textcolor{preprocessor}{\#define\ SAU\_RBAR\_BADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01693\ \textcolor{preprocessor}{\#define\ SAU\_RBAR\_BADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ SAU\_RBAR\_BADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01694\ }
\DoxyCodeLine{01695\ \textcolor{comment}{/*\ SAU\ Region\ Limit\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01696\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_LADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01697\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_LADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ SAU\_RLAR\_LADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01698\ }
\DoxyCodeLine{01699\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_NSC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01700\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_NSC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_RLAR\_NSC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01701\ }
\DoxyCodeLine{01702\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01703\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SAU\_RLAR\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01704\ }
\DoxyCodeLine{01705\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01706\ }
\DoxyCodeLine{01707\ \textcolor{comment}{/*\ Secure\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01708\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01709\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_LSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01710\ }
\DoxyCodeLine{01711\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_SFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01712\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_SFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_SFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01713\ }
\DoxyCodeLine{01714\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01715\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01716\ }
\DoxyCodeLine{01717\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVTRAN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01718\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVTRAN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVTRAN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01719\ }
\DoxyCodeLine{01720\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_AUVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01721\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_AUVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_AUVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01722\ }
\DoxyCodeLine{01723\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01724\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01725\ }
\DoxyCodeLine{01726\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVIS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01727\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVIS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVIS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01728\ }
\DoxyCodeLine{01729\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01730\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SAU\_SFSR\_INVEP\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01731\ }
\DoxyCodeLine{01733\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01734\ }
\DoxyCodeLine{01735\ }
\DoxyCodeLine{01742\ }
\DoxyCodeLine{01746\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01747\ \{}
\DoxyCodeLine{01748\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01749\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf1b708c5e413739150df3d16ca3b7061}{FPCCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01750\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga55263b468d0f8e11ac77aec9ff87c820}{FPCAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01751\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga58d1989664a06db6ec2e122eefa9f04a}{FPDSCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01752\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4f19014defe6033d070b80af19ef627c}{MVFR0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01753\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga66f8cfa49a423b480001a4e101bf842d}{MVFR1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01754\ \}\ \mbox{\hyperlink{struct_f_p_u___type}{FPU\_Type}};}
\DoxyCodeLine{01755\ }
\DoxyCodeLine{01756\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01757\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01758\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_ASPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01759\ }
\DoxyCodeLine{01760\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01761\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01762\ }
\DoxyCodeLine{01763\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPENS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01764\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPENS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPENS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01765\ }
\DoxyCodeLine{01766\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01767\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_CLRONRET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01768\ }
\DoxyCodeLine{01769\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRETS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01770\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRETS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_CLRONRETS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01771\ }
\DoxyCodeLine{01772\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_TS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01773\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_TS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_TS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01774\ }
\DoxyCodeLine{01775\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_UFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01776\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_UFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_UFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01777\ }
\DoxyCodeLine{01778\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SPLIMVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01779\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SPLIMVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_SPLIMVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01780\ }
\DoxyCodeLine{01781\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01782\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MONRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01783\ }
\DoxyCodeLine{01784\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01785\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_SFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01786\ }
\DoxyCodeLine{01787\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01788\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_BFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01789\ }
\DoxyCodeLine{01790\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01791\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MMRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01792\ }
\DoxyCodeLine{01793\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01794\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_HFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01795\ }
\DoxyCodeLine{01796\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01797\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_THREAD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01798\ }
\DoxyCodeLine{01799\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_S\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01800\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_S\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_S\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01801\ }
\DoxyCodeLine{01802\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01803\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_USER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01804\ }
\DoxyCodeLine{01805\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01806\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ FPU\_FPCCR\_LSPACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01807\ }
\DoxyCodeLine{01808\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01809\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01810\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFFUL\ <<\ FPU\_FPCAR\_ADDRESS\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01811\ }
\DoxyCodeLine{01812\ \textcolor{comment}{/*\ Floating-\/Point\ Default\ Status\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01813\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01814\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_AHP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01815\ }
\DoxyCodeLine{01816\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01817\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_DN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01818\ }
\DoxyCodeLine{01819\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01820\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_FZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01821\ }
\DoxyCodeLine{01822\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01823\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ FPU\_FPDSCR\_RMode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01824\ }
\DoxyCodeLine{01825\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 0\ Definitions\ */}}
\DoxyCodeLine{01826\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos\ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01827\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01828\ }
\DoxyCodeLine{01829\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01830\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Short\_vectors\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01831\ }
\DoxyCodeLine{01832\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Pos\ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01833\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Square\_root\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01834\ }
\DoxyCodeLine{01835\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01836\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Divide\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01837\ }
\DoxyCodeLine{01838\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos\ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01839\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01840\ }
\DoxyCodeLine{01841\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Pos\ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01842\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Double\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01843\ }
\DoxyCodeLine{01844\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Pos\ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01845\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Single\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01846\ }
\DoxyCodeLine{01847\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos\ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01848\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Msk\ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01849\ }
\DoxyCodeLine{01850\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 1\ Definitions\ */}}
\DoxyCodeLine{01851\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos\ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01852\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Msk\ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01853\ }
\DoxyCodeLine{01854\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01855\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_HPFP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01856\ }
\DoxyCodeLine{01857\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01858\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_D\_NaN\_mode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01859\ }
\DoxyCodeLine{01860\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01861\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR1\_FtZ\_mode\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01862\ }
\DoxyCodeLine{01864\ }
\DoxyCodeLine{01865\ }
\DoxyCodeLine{01872\ }
\DoxyCodeLine{01876\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01877\ \{}
\DoxyCodeLine{01878\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad63554e4650da91a8e79929cbb63db66}{DHCSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01879\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf907cf64577eaf927dac6787df6dd98b}{DCRSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01880\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaab3cc92ef07bc1f04b3a3aa6db2c2d55}{DCRDR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01881\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaeb3126abc4c258a858f21f356c0df6ee}{DEMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01882\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01883\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga1b319a8279b9ff2572ab5391dba5bb88}{DAUTHCTRL}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01884\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad9fa5e915e038e20b9be88d54d432fb8}{DSCSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01885\ \}\ \mbox{\hyperlink{struct_core_debug___type}{CoreDebug\_Type}};}
\DoxyCodeLine{01886\ }
\DoxyCodeLine{01887\ \textcolor{comment}{/*\ Debug\ Halting\ Control\ and\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01888\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_DBGKEY\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01889\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_DBGKEY\_Msk\ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ CoreDebug\_DHCSR\_DBGKEY\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01890\ }
\DoxyCodeLine{01891\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESTART\_ST\_Pos\ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01892\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESTART\_ST\_Msk\ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_RESTART\_ST\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01893\ }
\DoxyCodeLine{01894\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Pos\ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01895\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01896\ }
\DoxyCodeLine{01897\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Pos\ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01898\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Msk\ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01899\ }
\DoxyCodeLine{01900\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_LOCKUP\_Pos\ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01901\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_LOCKUP\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_LOCKUP\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01902\ }
\DoxyCodeLine{01903\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_SLEEP\_Pos\ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01904\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_SLEEP\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_SLEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01905\ }
\DoxyCodeLine{01906\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_HALT\_Pos\ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01907\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_HALT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_HALT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01908\ }
\DoxyCodeLine{01909\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_REGRDY\_Pos\ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01910\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_REGRDY\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_REGRDY\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01911\ }
\DoxyCodeLine{01912\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Pos\ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01913\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Msk\ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01914\ }
\DoxyCodeLine{01915\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_MASKINTS\_Pos\ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01916\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_MASKINTS\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_MASKINTS\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01917\ }
\DoxyCodeLine{01918\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_STEP\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01919\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_STEP\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_STEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01920\ }
\DoxyCodeLine{01921\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_HALT\_Pos\ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01922\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_HALT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_HALT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01923\ }
\DoxyCodeLine{01924\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Pos\ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01925\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Msk\ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01926\ }
\DoxyCodeLine{01927\ \textcolor{comment}{/*\ Debug\ Core\ Register\ Selector\ Register\ Definitions\ */}}
\DoxyCodeLine{01928\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGWnR\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01929\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGWnR\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DCRSR\_REGWnR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01930\ }
\DoxyCodeLine{01931\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGSEL\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01932\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGSEL\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ CoreDebug\_DCRSR\_REGSEL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01933\ }
\DoxyCodeLine{01934\ \textcolor{comment}{/*\ Debug\ Exception\ and\ Monitor\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01935\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_TRCENA\_Pos\ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01936\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_TRCENA\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_TRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01937\ }
\DoxyCodeLine{01938\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_REQ\_Pos\ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01939\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_REQ\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_REQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01940\ }
\DoxyCodeLine{01941\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_STEP\_Pos\ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01942\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_STEP\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_STEP\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01943\ }
\DoxyCodeLine{01944\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_PEND\_Pos\ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01945\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_PEND\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_PEND\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01946\ }
\DoxyCodeLine{01947\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_EN\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01948\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_EN\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_EN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01949\ }
\DoxyCodeLine{01950\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_HARDERR\_Pos\ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01951\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_HARDERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_HARDERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01952\ }
\DoxyCodeLine{01953\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_INTERR\_Pos\ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01954\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_INTERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_INTERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01955\ }
\DoxyCodeLine{01956\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_BUSERR\_Pos\ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01957\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_BUSERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_BUSERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01958\ }
\DoxyCodeLine{01959\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_STATERR\_Pos\ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01960\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_STATERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_STATERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01961\ }
\DoxyCodeLine{01962\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CHKERR\_Pos\ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01963\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CHKERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_CHKERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01964\ }
\DoxyCodeLine{01965\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Pos\ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01966\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01967\ }
\DoxyCodeLine{01968\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_MMERR\_Pos\ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01969\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_MMERR\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_MMERR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01970\ }
\DoxyCodeLine{01971\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CORERESET\_Pos\ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01972\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CORERESET\_Msk\ \ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DEMCR\_VC\_CORERESET\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01973\ }
\DoxyCodeLine{01974\ \textcolor{comment}{/*\ Debug\ Authentication\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01975\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_INTSPNIDEN\_Pos\ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01976\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_INTSPNIDEN\_Msk\ (1UL\ <<\ CoreDebug\_DAUTHCTRL\_INTSPNIDEN\_Pos)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01977\ }
\DoxyCodeLine{01978\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_SPNIDENSEL\_Pos\ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01979\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_SPNIDENSEL\_Msk\ (1UL\ <<\ CoreDebug\_DAUTHCTRL\_SPNIDENSEL\_Pos)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01980\ }
\DoxyCodeLine{01981\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_INTSPIDEN\_Pos\ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01982\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_INTSPIDEN\_Msk\ \ (1UL\ <<\ CoreDebug\_DAUTHCTRL\_INTSPIDEN\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01983\ }
\DoxyCodeLine{01984\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_SPIDENSEL\_Pos\ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01985\ \textcolor{preprocessor}{\#define\ CoreDebug\_DAUTHCTRL\_SPIDENSEL\_Msk\ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DAUTHCTRL\_SPIDENSEL\_Pos*/}\textcolor{preprocessor}{)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01986\ }
\DoxyCodeLine{01987\ \textcolor{comment}{/*\ Debug\ Security\ Control\ and\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01988\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_CDS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01989\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_CDS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DSCSR\_CDS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01990\ }
\DoxyCodeLine{01991\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_SBRSEL\_Pos\ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01992\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_SBRSEL\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DSCSR\_SBRSEL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01993\ }
\DoxyCodeLine{01994\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_SBRSELEN\_Pos\ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01995\ \textcolor{preprocessor}{\#define\ CoreDebug\_DSCSR\_SBRSELEN\_Msk\ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DSCSR\_SBRSELEN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01996\ }
\DoxyCodeLine{01998\ }
\DoxyCodeLine{01999\ }
\DoxyCodeLine{02006\ }
\DoxyCodeLine{02013\ \textcolor{preprocessor}{\#define\ \_VAL2FLD(field,\ value)\ \ \ \ (((uint32\_t)(value)\ <<\ field\ \#\#\ \_Pos)\ \&\ field\ \#\#\ \_Msk)}}
\DoxyCodeLine{02014\ }
\DoxyCodeLine{02021\ \textcolor{preprocessor}{\#define\ \_FLD2VAL(field,\ value)\ \ \ \ (((uint32\_t)(value)\ \&\ field\ \#\#\ \_Msk)\ >>\ field\ \#\#\ \_Pos)}}
\DoxyCodeLine{02022\ }
\DoxyCodeLine{02024\ }
\DoxyCodeLine{02025\ }
\DoxyCodeLine{02032\ }
\DoxyCodeLine{02033\ \textcolor{comment}{/*\ Memory\ mapping\ of\ Core\ Hardware\ */}}
\DoxyCodeLine{02034\ \textcolor{preprocessor}{\ \ \#define\ SCS\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE000E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02035\ \textcolor{preprocessor}{\ \ \#define\ ITM\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0000000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02036\ \textcolor{preprocessor}{\ \ \#define\ DWT\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0001000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02037\ \textcolor{preprocessor}{\ \ \#define\ TPI\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0040000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02038\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\_BASE\ \ \ \ \ \ (0xE000EDF0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02039\ \textcolor{preprocessor}{\ \ \#define\ SysTick\_BASE\ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0010UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02040\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_BASE\ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02041\ \textcolor{preprocessor}{\ \ \#define\ SCB\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02042\ }
\DoxyCodeLine{02043\ \textcolor{preprocessor}{\ \ \#define\ SCnSCB\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCnSCB\_Type\ \ \ \ *)\ \ \ \ \ SCS\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02044\ \textcolor{preprocessor}{\ \ \#define\ SCB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCB\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SCB\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02045\ \textcolor{preprocessor}{\ \ \#define\ SysTick\ \ \ \ \ \ \ \ \ \ \ \ \ ((SysTick\_Type\ \ \ *)\ \ \ \ \ SysTick\_BASE\ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02046\ \textcolor{preprocessor}{\ \ \#define\ NVIC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((NVIC\_Type\ \ \ \ \ \ *)\ \ \ \ \ NVIC\_BASE\ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02047\ \textcolor{preprocessor}{\ \ \#define\ ITM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ITM\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ ITM\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02048\ \textcolor{preprocessor}{\ \ \#define\ DWT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((DWT\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ DWT\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02049\ \textcolor{preprocessor}{\ \ \#define\ TPI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TPI\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ TPI\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02050\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\ \ \ \ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE\ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02051\ }
\DoxyCodeLine{02052\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02053\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\_BASE\ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D90UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02054\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02055\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02056\ }
\DoxyCodeLine{02057\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}}
\DoxyCodeLine{02058\ \textcolor{preprocessor}{\ \ \ \ \#define\ SAU\_BASE\ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0DD0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02059\ \textcolor{preprocessor}{\ \ \ \ \#define\ SAU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SAU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SAU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02060\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02061\ }
\DoxyCodeLine{02062\ \textcolor{preprocessor}{\ \ \#define\ FPU\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02063\ \textcolor{preprocessor}{\ \ \#define\ FPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((FPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ FPU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02064\ }
\DoxyCodeLine{02065\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}}
\DoxyCodeLine{02066\ \textcolor{preprocessor}{\ \ \#define\ SCS\_BASE\_NS\ \ \ \ \ \ \ \ \ (0xE002E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02067\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\_BASE\_NS\ \ \ (0xE002EDF0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02068\ \textcolor{preprocessor}{\ \ \#define\ SysTick\_BASE\_NS\ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0010UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02069\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_BASE\_NS\ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02070\ \textcolor{preprocessor}{\ \ \#define\ SCB\_BASE\_NS\ \ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02071\ }
\DoxyCodeLine{02072\ \textcolor{preprocessor}{\ \ \#define\ SCnSCB\_NS\ \ \ \ \ \ \ \ \ \ \ ((SCnSCB\_Type\ \ \ \ *)\ \ \ \ \ SCS\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02073\ \textcolor{preprocessor}{\ \ \#define\ SCB\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCB\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SCB\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02074\ \textcolor{preprocessor}{\ \ \#define\ SysTick\_NS\ \ \ \ \ \ \ \ \ \ ((SysTick\_Type\ \ \ *)\ \ \ \ \ SysTick\_BASE\_NS\ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02075\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ ((NVIC\_Type\ \ \ \ \ \ *)\ \ \ \ \ NVIC\_BASE\_NS\ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02076\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\_NS\ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE\_NS)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02077\ }
\DoxyCodeLine{02078\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02079\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\_BASE\_NS\ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0D90UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02080\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\_NS\ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02081\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02082\ }
\DoxyCodeLine{02083\ \textcolor{preprocessor}{\ \ \#define\ FPU\_BASE\_NS\ \ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02084\ \textcolor{preprocessor}{\ \ \#define\ FPU\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((FPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ FPU\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02085\ }
\DoxyCodeLine{02086\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02088\ }
\DoxyCodeLine{02089\ }
\DoxyCodeLine{02090\ }
\DoxyCodeLine{02091\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{02092\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hardware\ Abstraction\ Layer}}
\DoxyCodeLine{02093\ \textcolor{comment}{\ \ Core\ Function\ Interface\ contains:}}
\DoxyCodeLine{02094\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Functions}}
\DoxyCodeLine{02095\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Functions}}
\DoxyCodeLine{02096\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Functions}}
\DoxyCodeLine{02097\ \textcolor{comment}{\ \ -\/\ Core\ Register\ Access\ Functions}}
\DoxyCodeLine{02098\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{02102\ }
\DoxyCodeLine{02103\ }
\DoxyCodeLine{02104\ }
\DoxyCodeLine{02105\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ NVIC\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02112\ }
\DoxyCodeLine{02113\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_NVIC\_VIRTUAL}}
\DoxyCodeLine{02114\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02115\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_nvic\_virtual.h"{}}}
\DoxyCodeLine{02116\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02117\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02118\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02119\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriorityGrouping\ \ \ \ \_\_NVIC\_SetPriorityGrouping}}
\DoxyCodeLine{02120\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriorityGrouping\ \ \ \ \_\_NVIC\_GetPriorityGrouping}}
\DoxyCodeLine{02121\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_EnableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_EnableIRQ}}
\DoxyCodeLine{02122\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetEnableIRQ\ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetEnableIRQ}}
\DoxyCodeLine{02123\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_DisableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_DisableIRQ}}
\DoxyCodeLine{02124\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPendingIRQ}}
\DoxyCodeLine{02125\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPendingIRQ}}
\DoxyCodeLine{02126\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_ClearPendingIRQ\ \ \ \ \ \ \ \ \_\_NVIC\_ClearPendingIRQ}}
\DoxyCodeLine{02127\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetActive\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetActive}}
\DoxyCodeLine{02128\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPriority}}
\DoxyCodeLine{02129\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPriority}}
\DoxyCodeLine{02130\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SystemReset\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SystemReset}}
\DoxyCodeLine{02131\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CMSIS\_NVIC\_VIRTUAL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02132\ }
\DoxyCodeLine{02133\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_VECTAB\_VIRTUAL}}
\DoxyCodeLine{02134\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02135\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_vectab\_virtual.h"{}}}
\DoxyCodeLine{02136\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02137\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02138\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02139\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetVector}}
\DoxyCodeLine{02140\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetVector}}
\DoxyCodeLine{02141\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ (CMSIS\_VECTAB\_VIRTUAL)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02142\ }
\DoxyCodeLine{02143\ \textcolor{preprocessor}{\#define\ NVIC\_USER\_IRQ\_OFFSET\ \ \ \ \ \ \ \ \ \ 16}}
\DoxyCodeLine{02144\ }
\DoxyCodeLine{02145\ }
\DoxyCodeLine{02146\ }
\DoxyCodeLine{02156\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gafc94dcbaee03e4746ade1f5bb9aaa56d}{\_\_NVIC\_SetPriorityGrouping}}(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{02157\ \{}
\DoxyCodeLine{02158\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{02159\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02160\ }
\DoxyCodeLine{02161\ \ \ reg\_value\ \ =\ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{02162\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02163\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{02164\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{02165\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priorty\ group\ */}}
\DoxyCodeLine{02166\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ =\ \ reg\_value;}
\DoxyCodeLine{02167\ \}}
\DoxyCodeLine{02168\ }
\DoxyCodeLine{02169\ }
\DoxyCodeLine{02175\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga9b894af672df4373eb637f8288845c05}{\_\_NVIC\_GetPriorityGrouping}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02176\ \{}
\DoxyCodeLine{02177\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
\DoxyCodeLine{02178\ \}}
\DoxyCodeLine{02179\ }
\DoxyCodeLine{02180\ }
\DoxyCodeLine{02187\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga71227e1376cde11eda03fcb62f1b33ea}{\_\_NVIC\_EnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02188\ \{}
\DoxyCodeLine{02189\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02190\ \ \ \{}
\DoxyCodeLine{02191\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02192\ \ \ \}}
\DoxyCodeLine{02193\ \}}
\DoxyCodeLine{02194\ }
\DoxyCodeLine{02195\ }
\DoxyCodeLine{02204\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaaeb5e7cc0eaad4e2817272e7bf742083}{\_\_NVIC\_GetEnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02205\ \{}
\DoxyCodeLine{02206\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02207\ \ \ \{}
\DoxyCodeLine{02208\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02209\ \ \ \}}
\DoxyCodeLine{02210\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02211\ \ \ \{}
\DoxyCodeLine{02212\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02213\ \ \ \}}
\DoxyCodeLine{02214\ \}}
\DoxyCodeLine{02215\ }
\DoxyCodeLine{02216\ }
\DoxyCodeLine{02223\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae016e4c1986312044ee768806537d52f}{\_\_NVIC\_DisableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02224\ \{}
\DoxyCodeLine{02225\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02226\ \ \ \{}
\DoxyCodeLine{02227\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02228\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02229\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02230\ \ \ \}}
\DoxyCodeLine{02231\ \}}
\DoxyCodeLine{02232\ }
\DoxyCodeLine{02233\ }
\DoxyCodeLine{02242\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga5a92ca5fa801ad7adb92be7257ab9694}{\_\_NVIC\_GetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02243\ \{}
\DoxyCodeLine{02244\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02245\ \ \ \{}
\DoxyCodeLine{02246\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02247\ \ \ \}}
\DoxyCodeLine{02248\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02249\ \ \ \{}
\DoxyCodeLine{02250\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02251\ \ \ \}}
\DoxyCodeLine{02252\ \}}
\DoxyCodeLine{02253\ }
\DoxyCodeLine{02254\ }
\DoxyCodeLine{02261\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaabefdd4b790b9a7308929938c0c1e1ad}{\_\_NVIC\_SetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02262\ \{}
\DoxyCodeLine{02263\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02264\ \ \ \{}
\DoxyCodeLine{02265\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02266\ \ \ \}}
\DoxyCodeLine{02267\ \}}
\DoxyCodeLine{02268\ }
\DoxyCodeLine{02269\ }
\DoxyCodeLine{02276\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga562a86dbdf14827d0fee8fdafb04d191}{\_\_NVIC\_ClearPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02277\ \{}
\DoxyCodeLine{02278\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02279\ \ \ \{}
\DoxyCodeLine{02280\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02281\ \ \ \}}
\DoxyCodeLine{02282\ \}}
\DoxyCodeLine{02283\ }
\DoxyCodeLine{02284\ }
\DoxyCodeLine{02293\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaa2837003c28c45abf193fe5e8d27f593}{\_\_NVIC\_GetActive}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02294\ \{}
\DoxyCodeLine{02295\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02296\ \ \ \{}
\DoxyCodeLine{02297\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02298\ \ \ \}}
\DoxyCodeLine{02299\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02300\ \ \ \{}
\DoxyCodeLine{02301\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02302\ \ \ \}}
\DoxyCodeLine{02303\ \}}
\DoxyCodeLine{02304\ }
\DoxyCodeLine{02305\ }
\DoxyCodeLine{02306\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02315\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_GetTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02316\ \{}
\DoxyCodeLine{02317\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02318\ \ \ \{}
\DoxyCodeLine{02319\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02320\ \ \ \}}
\DoxyCodeLine{02321\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02322\ \ \ \{}
\DoxyCodeLine{02323\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02324\ \ \ \}}
\DoxyCodeLine{02325\ \}}
\DoxyCodeLine{02326\ }
\DoxyCodeLine{02327\ }
\DoxyCodeLine{02336\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_SetTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02337\ \{}
\DoxyCodeLine{02338\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02339\ \ \ \{}
\DoxyCodeLine{02340\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ |=\ \ ((uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)));}
\DoxyCodeLine{02341\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02342\ \ \ \}}
\DoxyCodeLine{02343\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02344\ \ \ \{}
\DoxyCodeLine{02345\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02346\ \ \ \}}
\DoxyCodeLine{02347\ \}}
\DoxyCodeLine{02348\ }
\DoxyCodeLine{02349\ }
\DoxyCodeLine{02358\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_ClearTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02359\ \{}
\DoxyCodeLine{02360\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02361\ \ \ \{}
\DoxyCodeLine{02362\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&=\ \string~((uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)));}
\DoxyCodeLine{02363\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02364\ \ \ \}}
\DoxyCodeLine{02365\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02366\ \ \ \{}
\DoxyCodeLine{02367\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02368\ \ \ \}}
\DoxyCodeLine{02369\ \}}
\DoxyCodeLine{02370\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02371\ }
\DoxyCodeLine{02372\ }
\DoxyCodeLine{02382\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga505338e23563a9c074910fb14e7d45fd}{\_\_NVIC\_SetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{02383\ \{}
\DoxyCodeLine{02384\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02385\ \ \ \{}
\DoxyCodeLine{02386\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02387\ \ \ \}}
\DoxyCodeLine{02388\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02389\ \ \ \{}
\DoxyCodeLine{02390\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02391\ \ \ \}}
\DoxyCodeLine{02392\ \}}
\DoxyCodeLine{02393\ }
\DoxyCodeLine{02394\ }
\DoxyCodeLine{02404\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaeb9dc99c8e7700668813144261b0bc73}{\_\_NVIC\_GetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02405\ \{}
\DoxyCodeLine{02406\ }
\DoxyCodeLine{02407\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02408\ \ \ \{}
\DoxyCodeLine{02409\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02410\ \ \ \}}
\DoxyCodeLine{02411\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02412\ \ \ \{}
\DoxyCodeLine{02413\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02414\ \ \ \}}
\DoxyCodeLine{02415\ \}}
\DoxyCodeLine{02416\ }
\DoxyCodeLine{02417\ }
\DoxyCodeLine{02429\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gadb94ac5d892b376e4f3555ae0418ebac}{NVIC\_EncodePriority}}\ (uint32\_t\ PriorityGroup,\ uint32\_t\ PreemptPriority,\ uint32\_t\ SubPriority)}
\DoxyCodeLine{02430\ \{}
\DoxyCodeLine{02431\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02432\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02433\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02434\ }
\DoxyCodeLine{02435\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02436\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02437\ }
\DoxyCodeLine{02438\ \ \ \textcolor{keywordflow}{return}\ (}
\DoxyCodeLine{02439\ \ \ \ \ \ \ \ \ \ \ \ ((PreemptPriority\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL))\ <<\ SubPriorityBits)\ |}
\DoxyCodeLine{02440\ \ \ \ \ \ \ \ \ \ \ \ ((SubPriority\ \ \ \ \ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL)))}
\DoxyCodeLine{02441\ \ \ \ \ \ \ \ \ \ );}
\DoxyCodeLine{02442\ \}}
\DoxyCodeLine{02443\ }
\DoxyCodeLine{02444\ }
\DoxyCodeLine{02456\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga3387607fd8a1a32cccd77d2ac672dd96}{NVIC\_DecodePriority}}\ (uint32\_t\ Priority,\ uint32\_t\ PriorityGroup,\ uint32\_t*\ \textcolor{keyword}{const}\ pPreemptPriority,\ uint32\_t*\ \textcolor{keyword}{const}\ pSubPriority)}
\DoxyCodeLine{02457\ \{}
\DoxyCodeLine{02458\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02459\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02460\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02461\ }
\DoxyCodeLine{02462\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02463\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02464\ }
\DoxyCodeLine{02465\ \ \ *pPreemptPriority\ =\ (Priority\ >>\ SubPriorityBits)\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL);}
\DoxyCodeLine{02466\ \ \ *pSubPriority\ \ \ \ \ =\ (Priority\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL);}
\DoxyCodeLine{02467\ \}}
\DoxyCodeLine{02468\ }
\DoxyCodeLine{02469\ }
\DoxyCodeLine{02479\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0df355460bc1783d58f9d72ee4884208}{\_\_NVIC\_SetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ vector)}
\DoxyCodeLine{02480\ \{}
\DoxyCodeLine{02481\ \ \ uint32\_t\ *vectors\ =\ (uint32\_t\ *)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02482\ \ \ vectors[(int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET]\ =\ vector;}
\DoxyCodeLine{02483\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02484\ \}}
\DoxyCodeLine{02485\ }
\DoxyCodeLine{02486\ }
\DoxyCodeLine{02495\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga44b665d2afb708121d9b10c76ff00ee5}{\_\_NVIC\_GetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02496\ \{}
\DoxyCodeLine{02497\ \ \ uint32\_t\ *vectors\ =\ (uint32\_t\ *)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02498\ \ \ \textcolor{keywordflow}{return}\ vectors[(int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET];}
\DoxyCodeLine{02499\ \}}
\DoxyCodeLine{02500\ }
\DoxyCodeLine{02501\ }
\DoxyCodeLine{02506\ \_\_NO\_RETURN\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0d9aa2d30fa54b41eb780c16e35b676c}{\_\_NVIC\_SystemReset}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02507\ \{}
\DoxyCodeLine{02508\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ all\ outstanding\ memory\ accesses\ included}}
\DoxyCodeLine{02509\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ buffered\ write\ are\ completed\ before\ reset\ */}}
\DoxyCodeLine{02510\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \ =\ (uint32\_t)((0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ \ \ \ |}
\DoxyCodeLine{02511\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ |}
\DoxyCodeLine{02512\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaae1181119559a5bd36e62afa373fa720}{SCB\_AIRCR\_SYSRESETREQ\_Msk}}\ \ \ \ );\ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Keep\ priority\ group\ unchanged\ */}}
\DoxyCodeLine{02513\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ completion\ of\ memory\ access\ */}}
\DoxyCodeLine{02514\ }
\DoxyCodeLine{02515\ \ \ \textcolor{keywordflow}{for}(;;)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ wait\ until\ reset\ */}}
\DoxyCodeLine{02516\ \ \ \{}
\DoxyCodeLine{02517\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{02518\ \ \ \}}
\DoxyCodeLine{02519\ \}}
\DoxyCodeLine{02520\ }
\DoxyCodeLine{02521\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02531\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPriorityGrouping\_NS(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{02532\ \{}
\DoxyCodeLine{02533\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{02534\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02535\ }
\DoxyCodeLine{02536\ \ \ reg\_value\ \ =\ \ SCB\_NS-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{02537\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02538\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{02539\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{02540\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priorty\ group\ */}}
\DoxyCodeLine{02541\ \ \ SCB\_NS-\/>AIRCR\ =\ \ reg\_value;}
\DoxyCodeLine{02542\ \}}
\DoxyCodeLine{02543\ }
\DoxyCodeLine{02544\ }
\DoxyCodeLine{02550\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPriorityGrouping\_NS(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02551\ \{}
\DoxyCodeLine{02552\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((SCB\_NS-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
\DoxyCodeLine{02553\ \}}
\DoxyCodeLine{02554\ }
\DoxyCodeLine{02555\ }
\DoxyCodeLine{02562\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_EnableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02563\ \{}
\DoxyCodeLine{02564\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02565\ \ \ \{}
\DoxyCodeLine{02566\ \ \ \ \ NVIC\_NS-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02567\ \ \ \}}
\DoxyCodeLine{02568\ \}}
\DoxyCodeLine{02569\ }
\DoxyCodeLine{02570\ }
\DoxyCodeLine{02579\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetEnableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02580\ \{}
\DoxyCodeLine{02581\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02582\ \ \ \{}
\DoxyCodeLine{02583\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02584\ \ \ \}}
\DoxyCodeLine{02585\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02586\ \ \ \{}
\DoxyCodeLine{02587\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02588\ \ \ \}}
\DoxyCodeLine{02589\ \}}
\DoxyCodeLine{02590\ }
\DoxyCodeLine{02591\ }
\DoxyCodeLine{02598\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_DisableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02599\ \{}
\DoxyCodeLine{02600\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02601\ \ \ \{}
\DoxyCodeLine{02602\ \ \ \ \ NVIC\_NS-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02603\ \ \ \}}
\DoxyCodeLine{02604\ \}}
\DoxyCodeLine{02605\ }
\DoxyCodeLine{02606\ }
\DoxyCodeLine{02615\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02616\ \{}
\DoxyCodeLine{02617\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02618\ \ \ \{}
\DoxyCodeLine{02619\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02620\ \ \ \}}
\DoxyCodeLine{02621\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02622\ \ \ \{}
\DoxyCodeLine{02623\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02624\ \ \ \}}
\DoxyCodeLine{02625\ \}}
\DoxyCodeLine{02626\ }
\DoxyCodeLine{02627\ }
\DoxyCodeLine{02634\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02635\ \{}
\DoxyCodeLine{02636\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02637\ \ \ \{}
\DoxyCodeLine{02638\ \ \ \ \ NVIC\_NS-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02639\ \ \ \}}
\DoxyCodeLine{02640\ \}}
\DoxyCodeLine{02641\ }
\DoxyCodeLine{02642\ }
\DoxyCodeLine{02649\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_ClearPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02650\ \{}
\DoxyCodeLine{02651\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02652\ \ \ \{}
\DoxyCodeLine{02653\ \ \ \ \ NVIC\_NS-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02654\ \ \ \}}
\DoxyCodeLine{02655\ \}}
\DoxyCodeLine{02656\ }
\DoxyCodeLine{02657\ }
\DoxyCodeLine{02666\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetActive\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02667\ \{}
\DoxyCodeLine{02668\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02669\ \ \ \{}
\DoxyCodeLine{02670\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02671\ \ \ \}}
\DoxyCodeLine{02672\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02673\ \ \ \{}
\DoxyCodeLine{02674\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02675\ \ \ \}}
\DoxyCodeLine{02676\ \}}
\DoxyCodeLine{02677\ }
\DoxyCodeLine{02678\ }
\DoxyCodeLine{02688\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPriority\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{02689\ \{}
\DoxyCodeLine{02690\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02691\ \ \ \{}
\DoxyCodeLine{02692\ \ \ \ \ NVIC\_NS-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02693\ \ \ \}}
\DoxyCodeLine{02694\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02695\ \ \ \{}
\DoxyCodeLine{02696\ \ \ \ \ SCB\_NS-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02697\ \ \ \}}
\DoxyCodeLine{02698\ \}}
\DoxyCodeLine{02699\ }
\DoxyCodeLine{02700\ }
\DoxyCodeLine{02709\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPriority\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02710\ \{}
\DoxyCodeLine{02711\ }
\DoxyCodeLine{02712\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02713\ \ \ \{}
\DoxyCodeLine{02714\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)NVIC\_NS-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02715\ \ \ \}}
\DoxyCodeLine{02716\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02717\ \ \ \{}
\DoxyCodeLine{02718\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)SCB\_NS-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02719\ \ \ \}}
\DoxyCodeLine{02720\ \}}
\DoxyCodeLine{02721\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&(\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02722\ }
\DoxyCodeLine{02724\ }
\DoxyCodeLine{02725\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ MPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02726\ }
\DoxyCodeLine{02727\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02728\ }
\DoxyCodeLine{02729\ \textcolor{preprocessor}{\#include\ "{}mpu\_armv8.h"{}}}
\DoxyCodeLine{02730\ }
\DoxyCodeLine{02731\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02732\ }
\DoxyCodeLine{02733\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ FPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02740\ }
\DoxyCodeLine{02749\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga6bcad99ce80a0e7e4ddc6f2379081756}{SCB\_GetFPUType}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02750\ \{}
\DoxyCodeLine{02751\ \ \ uint32\_t\ mvfr0;}
\DoxyCodeLine{02752\ }
\DoxyCodeLine{02753\ \ \ mvfr0\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabc7c93f2594e85ece1e1a24f10591428}{FPU}}-\/>MVFR0;}
\DoxyCodeLine{02754\ \ \ \textcolor{keywordflow}{if}\ \ \ \ \ \ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x220U)}
\DoxyCodeLine{02755\ \ \ \{}
\DoxyCodeLine{02756\ \ \ \ \ \textcolor{keywordflow}{return}\ 2U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Double\ +\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02757\ \ \ \}}
\DoxyCodeLine{02758\ \ \ \textcolor{keywordflow}{else}\ \textcolor{keywordflow}{if}\ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x020U)}
\DoxyCodeLine{02759\ \ \ \{}
\DoxyCodeLine{02760\ \ \ \ \ \textcolor{keywordflow}{return}\ 1U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02761\ \ \ \}}
\DoxyCodeLine{02762\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02763\ \ \ \{}
\DoxyCodeLine{02764\ \ \ \ \ \textcolor{keywordflow}{return}\ 0U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ No\ FPU\ */}}
\DoxyCodeLine{02765\ \ \ \}}
\DoxyCodeLine{02766\ \}}
\DoxyCodeLine{02767\ }
\DoxyCodeLine{02768\ }
\DoxyCodeLine{02770\ }
\DoxyCodeLine{02771\ }
\DoxyCodeLine{02772\ }
\DoxyCodeLine{02773\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ SAU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02780\ }
\DoxyCodeLine{02781\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}}
\DoxyCodeLine{02782\ }
\DoxyCodeLine{02787\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_SAU\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02788\ \{}
\DoxyCodeLine{02789\ \ \ \ \ SAU-\/>CTRL\ |=\ \ (SAU\_CTRL\_ENABLE\_Msk);}
\DoxyCodeLine{02790\ \}}
\DoxyCodeLine{02791\ }
\DoxyCodeLine{02792\ }
\DoxyCodeLine{02793\ }
\DoxyCodeLine{02798\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_SAU\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02799\ \{}
\DoxyCodeLine{02800\ \ \ \ \ SAU-\/>CTRL\ \&=\ \string~(SAU\_CTRL\_ENABLE\_Msk);}
\DoxyCodeLine{02801\ \}}
\DoxyCodeLine{02802\ }
\DoxyCodeLine{02803\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02804\ }
\DoxyCodeLine{02806\ }
\DoxyCodeLine{02807\ }
\DoxyCodeLine{02808\ }
\DoxyCodeLine{02809\ }
\DoxyCodeLine{02810\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ \ SysTick\ function\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02817\ }
\DoxyCodeLine{02818\ \textcolor{preprocessor}{\#if\ defined\ (\_\_Vendor\_SysTickConfig)\ \&\&\ (\_\_Vendor\_SysTickConfig\ ==\ 0U)}}
\DoxyCodeLine{02819\ }
\DoxyCodeLine{02831\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae4e8f0238527c69f522029b93c8e5b78}{SysTick\_Config}}(uint32\_t\ ticks)}
\DoxyCodeLine{02832\ \{}
\DoxyCodeLine{02833\ \ \ \textcolor{keywordflow}{if}\ ((ticks\ -\/\ 1UL)\ >\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga265912a7962f0e1abd170336e579b1b1}{SysTick\_LOAD\_RELOAD\_Msk}})}
\DoxyCodeLine{02834\ \ \ \{}
\DoxyCodeLine{02835\ \ \ \ \ \textcolor{keywordflow}{return}\ (1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Reload\ value\ impossible\ */}}
\DoxyCodeLine{02836\ \ \ \}}
\DoxyCodeLine{02837\ }
\DoxyCodeLine{02838\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>LOAD\ \ =\ (uint32\_t)(ticks\ -\/\ 1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ set\ reload\ register\ */}}
\DoxyCodeLine{02839\ \ \ NVIC\_SetPriority\ (\mbox{\hyperlink{group___peripheral__interrupt__number__definition_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7}{SysTick\_IRQn}},\ (1UL\ <<\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ -\/\ 1UL);\ \textcolor{comment}{/*\ set\ Priority\ for\ Systick\ Interrupt\ */}}
\DoxyCodeLine{02840\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>VAL\ \ \ =\ 0UL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Load\ the\ SysTick\ Counter\ Value\ */}}
\DoxyCodeLine{02841\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>CTRL\ \ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa41d06039797423a46596bd313d57373}{SysTick\_CTRL\_CLKSOURCE\_Msk}}\ |}
\DoxyCodeLine{02842\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95bb984266ca764024836a870238a027}{SysTick\_CTRL\_TICKINT\_Msk}}\ \ \ |}
\DoxyCodeLine{02843\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga16c9fee0ed0235524bdeb38af328fd1f}{SysTick\_CTRL\_ENABLE\_Msk}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Enable\ SysTick\ IRQ\ and\ SysTick\ Timer\ */}}
\DoxyCodeLine{02844\ \ \ \textcolor{keywordflow}{return}\ (0UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Function\ successful\ */}}
\DoxyCodeLine{02845\ \}}
\DoxyCodeLine{02846\ }
\DoxyCodeLine{02847\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02860\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_SysTick\_Config\_NS(uint32\_t\ ticks)}
\DoxyCodeLine{02861\ \{}
\DoxyCodeLine{02862\ \ \ \textcolor{keywordflow}{if}\ ((ticks\ -\/\ 1UL)\ >\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga265912a7962f0e1abd170336e579b1b1}{SysTick\_LOAD\_RELOAD\_Msk}})}
\DoxyCodeLine{02863\ \ \ \{}
\DoxyCodeLine{02864\ \ \ \ \ \textcolor{keywordflow}{return}\ (1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Reload\ value\ impossible\ */}}
\DoxyCodeLine{02865\ \ \ \}}
\DoxyCodeLine{02866\ }
\DoxyCodeLine{02867\ \ \ SysTick\_NS-\/>LOAD\ \ =\ (uint32\_t)(ticks\ -\/\ 1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ set\ reload\ register\ */}}
\DoxyCodeLine{02868\ \ \ TZ\_NVIC\_SetPriority\_NS\ (\mbox{\hyperlink{group___peripheral__interrupt__number__definition_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7}{SysTick\_IRQn}},\ (1UL\ <<\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ -\/\ 1UL);\ \textcolor{comment}{/*\ set\ Priority\ for\ Systick\ Interrupt\ */}}
\DoxyCodeLine{02869\ \ \ SysTick\_NS-\/>VAL\ \ \ =\ 0UL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Load\ the\ SysTick\ Counter\ Value\ */}}
\DoxyCodeLine{02870\ \ \ SysTick\_NS-\/>CTRL\ \ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa41d06039797423a46596bd313d57373}{SysTick\_CTRL\_CLKSOURCE\_Msk}}\ |}
\DoxyCodeLine{02871\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95bb984266ca764024836a870238a027}{SysTick\_CTRL\_TICKINT\_Msk}}\ \ \ |}
\DoxyCodeLine{02872\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga16c9fee0ed0235524bdeb38af328fd1f}{SysTick\_CTRL\_ENABLE\_Msk}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Enable\ SysTick\ IRQ\ and\ SysTick\ Timer\ */}}
\DoxyCodeLine{02873\ \ \ \textcolor{keywordflow}{return}\ (0UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Function\ successful\ */}}
\DoxyCodeLine{02874\ \}}
\DoxyCodeLine{02875\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02876\ }
\DoxyCodeLine{02877\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02878\ }
\DoxyCodeLine{02880\ }
\DoxyCodeLine{02881\ }
\DoxyCodeLine{02882\ }
\DoxyCodeLine{02883\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ Debug\ In/Output\ function\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02890\ }
\DoxyCodeLine{02891\ \textcolor{keyword}{extern}\ \textcolor{keyword}{volatile}\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02892\ \textcolor{preprocessor}{\#define\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ITM\_RXBUFFER\_EMPTY\ \ ((int32\_t)0x5AA55AA5U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02893\ }
\DoxyCodeLine{02894\ }
\DoxyCodeLine{02903\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac90a497bd64286b84552c2c553d3419e}{ITM\_SendChar}}\ (uint32\_t\ ch)}
\DoxyCodeLine{02904\ \{}
\DoxyCodeLine{02905\ \ \ \textcolor{keywordflow}{if}\ (((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>TCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga7dd53e3bff24ac09d94e61cb595cb2d9}{ITM\_TCR\_ITMENA\_Msk}})\ !=\ 0UL)\ \&\&\ \ \ \ \ \ \textcolor{comment}{/*\ ITM\ enabled\ */}}
\DoxyCodeLine{02906\ \ \ \ \ \ \ ((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>TER\ \&\ 1UL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ !=\ 0UL)\ \ \ )\ \ \ \ \ \textcolor{comment}{/*\ ITM\ Port\ \#0\ enabled\ */}}
\DoxyCodeLine{02907\ \ \ \{}
\DoxyCodeLine{02908\ \ \ \ \ \textcolor{keywordflow}{while}\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>PORT[0U].u32\ ==\ 0UL)}
\DoxyCodeLine{02909\ \ \ \ \ \{}
\DoxyCodeLine{02910\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{02911\ \ \ \ \ \}}
\DoxyCodeLine{02912\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>PORT[0U].u8\ =\ (uint8\_t)ch;}
\DoxyCodeLine{02913\ \ \ \}}
\DoxyCodeLine{02914\ \ \ \textcolor{keywordflow}{return}\ (ch);}
\DoxyCodeLine{02915\ \}}
\DoxyCodeLine{02916\ }
\DoxyCodeLine{02917\ }
\DoxyCodeLine{02924\ \_\_STATIC\_INLINE\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac3ee2c30a1ac4ed34c8a866a17decd53}{ITM\_ReceiveChar}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02925\ \{}
\DoxyCodeLine{02926\ \ \ int32\_t\ ch\ =\ -\/1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ no\ character\ available\ */}}
\DoxyCodeLine{02927\ }
\DoxyCodeLine{02928\ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ !=\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}})}
\DoxyCodeLine{02929\ \ \ \{}
\DoxyCodeLine{02930\ \ \ \ \ ch\ =\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}};}
\DoxyCodeLine{02931\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ =\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}};\ \ \ \ \ \ \ \textcolor{comment}{/*\ ready\ for\ next\ character\ */}}
\DoxyCodeLine{02932\ \ \ \}}
\DoxyCodeLine{02933\ }
\DoxyCodeLine{02934\ \ \ \textcolor{keywordflow}{return}\ (ch);}
\DoxyCodeLine{02935\ \}}
\DoxyCodeLine{02936\ }
\DoxyCodeLine{02937\ }
\DoxyCodeLine{02944\ \_\_STATIC\_INLINE\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae61ce9ca5917735325cd93b0fb21dd29}{ITM\_CheckChar}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02945\ \{}
\DoxyCodeLine{02946\ }
\DoxyCodeLine{02947\ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ ==\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}})}
\DoxyCodeLine{02948\ \ \ \{}
\DoxyCodeLine{02949\ \ \ \ \ \textcolor{keywordflow}{return}\ (0);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ no\ character\ available\ */}}
\DoxyCodeLine{02950\ \ \ \}}
\DoxyCodeLine{02951\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02952\ \ \ \{}
\DoxyCodeLine{02953\ \ \ \ \ \textcolor{keywordflow}{return}\ (1);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ \ \ \ character\ available\ */}}
\DoxyCodeLine{02954\ \ \ \}}
\DoxyCodeLine{02955\ \}}
\DoxyCodeLine{02956\ }
\DoxyCodeLine{02958\ }
\DoxyCodeLine{02959\ }
\DoxyCodeLine{02960\ }
\DoxyCodeLine{02961\ }
\DoxyCodeLine{02962\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{02963\ \}}
\DoxyCodeLine{02964\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02965\ }
\DoxyCodeLine{02966\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CORE\_ARMV81MML\_H\_DEPENDANT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02967\ }
\DoxyCodeLine{02968\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CMSIS\_GENERIC\ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
